MC68EC060RC66 Freescale Semiconductor, MC68EC060RC66 Datasheet - Page 32
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MC68EC060RC66
Manufacturer Part Number
MC68EC060RC66
Description
IC MPU 32BIT 66MHZ 206-PGA
Manufacturer
Freescale Semiconductor
Specifications of MC68EC060RC66
Processor Type
M680x0 32-Bit
Speed
66MHz
Voltage
3.3V
Mounting Type
Surface Mount
Package / Case
206-PGA
Family Name
M68000
Device Core
ColdFire
Device Core Size
32b
Frequency (max)
66MHz
Instruction Set Architecture
RISC
Supply Voltage 1 (typ)
3.3V
Operating Supply Voltage (max)
3.465V
Operating Supply Voltage (min)
3.135V
Operating Temp Range
0C to 110C
Operating Temperature Classification
Commercial
Mounting
Through Hole
Pin Count
206
Package Type
PGA
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Features
-
Lead Free Status / Rohs Status
Compliant
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Introduction
1.4.2.2 INTEGER UNIT. The integer unit contains dual integer execution pipelines, inter-
face logic to the FPU, and control logic for data written to the data cache and MMU. The
superscalar design of the dual integer execution pipelines provide for simultaneous instruc-
tion execution, which allows for processing more than one instruction during each machine
clock cycle. The net effect of this is a software invisible pipeline capable of sustained exe-
cution rates of less than one machine clock cycle per instruction for the M68000 instruction
set.
The integer unit’s control logic pulls an instruction pair from the instruction buffer every
machine clock cycle, stopping only if the instruction information is not available or if an inte-
ger execution pipeline hold condition exists. The six stages in the dual integer execution
pipelines are:
The MC68060 is optimized for most integer instructions to execute in one machine clock
cycle. If during the instruction decode stage, the instruction is determined to be a floating-
point instruction, it will be passed to the FPU after the effective address calculate stage. If
data is to be written to either the on-chip caches or external memory after instruction execu-
tion, the write-back stage holds the data until memory is ready to receive it.
1.4.2.3 FLOATING-POINT UNIT. Floating-point math is distinguished from integer math,
which deals only with whole numbers and fixed decimal point locations. The IEEE-compat-
ible MC68060's FPU computes numeric calculations with a variable decimal point location.
Consolidating the FPU on-chip speeds up overall processing and eliminates the interfacing
overhead associated with external accelerators. The MC68060's FPU operates in parallel
with the integer unit. The FPU performs numeric calculations while the integer unit continues
integer processing.
The FPU has been optimized for the most frequently used instructions and data types to pro-
vide the highest possible performance. The FPU can also be disabled in software to reduce
system power consumption.
1-8
1. Decode (DS)—The instruction is fully decoded.
2. Effective Address Calculation (AG)—If the instruction calls for data from memory, the
3. Effective Address Fetch (OC)—Data is fetched from the memory location.
4. Integer Execution (EX)—The data is manipulated during execution.
5. Data Available (DA)—The result is available.
6. Write-Back (WB)—The resulting data is written back to on-chip caches or external
location of the data is calculated.
memory.
M68060 USER’S MANUAL
MOTOROLA
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