IP-NIOS Altera, IP-NIOS Datasheet - Page 275

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IP-NIOS

Manufacturer Part Number
IP-NIOS
Description
IP NIOS II MEGACORE
Manufacturer
Altera
Type
Licenser
Datasheets

Specifications of IP-NIOS

Processor Type
RISC 32-Bit
Lead Free Status / RoHS Status
Not applicable / Not applicable
Features
-
Package / Case
-
Mounting Type
-
Voltage
-
Speed
-
Chapter 8: Instruction Set Reference
Instruction Set Reference
sra
December 2010 Altera Corporation
Operation:
Assembler Syntax:
Example:
Description:
Usage:
Exceptions:
Instruction Type:
Instruction Fields:
31
30
29
A
28
27
26
25
24
B
rC ← (signed) rA >> ((unsigned) rB
sra rC, rA, rB
sra r6, r7, r8
Shifts rA right by the number of bits specified in rB
the result in rC. Bits 31–5 are ignored.
sra performs the signed >> operation of the C programming language.
None
R
A = Register index of operand rA
B = Register index of operand rB
C = Register index of operand rC
23
22
21
20
19
C
18
17
16
15
4..0
14
0x3b
)
13
12
11
4..0
(duplicating the sign bit), and then stores
10
9
0
8
Nios II Processor Reference Handbook
shift right arithmetic
7
6
5
4
0x3a
3
2
1
8–89
0

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