IP-NIOS Altera, IP-NIOS Datasheet - Page 45

• Manufacturer Part Number: IP-NIOS
• Description: IP NIOS II MEGACORE
• Manufacturer: Altera
• Type: Licenser

Specifications of IP-NIOS

• Processor Type: RISC 32-Bit
• Lead Free Status / RoHS Status: Not applicable / Not applicable
• Features: -
• Package / Case: -
• Mounting Type: -
• Voltage: -
• Speed: -

Chapter 2: Processor Architecture
Document Revision History
Table 2–8. Document Revision History (Part 2 of 2)
December 2010 Altera Corporation
November 2008
May 2008
October 2007
May 2007
March 2007
November 2006
May 2006
October 2005
May 2005
December 2004
September 2004
May 2004
Date
Version
8.1.0
7.2.0
7.1.0
7.0.0
6.1.0
6.0.0
5.1.0
5.0.0
8.0.0
1.2
1.1
1.0
■
■
■
Added MMU and MPU sections.
Maintenance release.
■
■
Maintenance release.
Described interrupt vector custom instruction.
■
■
Maintenance release.
Added tightly-coupled memory.
Added new control register ctl5.
Updates for Nios II 1.01 release.
Initial release.
Expanded floating-point instructions information.
Updated description of optional cpu_resetrequest and cpu_resettaken signals.
Added description of optional debugreq and debugack signals.
Added table of contents to Introduction section.
Added Referenced Documents section.
Added description of optional cpu_resetrequest and cpu_resettaken.
Added section on single precision floating-point instructions.
Changes
Nios II Processor Reference Handbook
2–23