NQ80331M667SL7NM Intel, NQ80331M667SL7NM Datasheet
NQ80331M667SL7NM
Specifications of NQ80331M667SL7NM
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NQ80331M667SL7NM Summary of contents
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... Two I C Bus Interface Units Warning: Intel Corporation products are not intended for use in life support appliances, devices or systems. Use of a Intel products in such applications without written consent is prohibited. Memory Controller — PC2700 Double Data Rate (DDR333) SDRAM — DDRII 400 SDRAM — ...
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... Contact your local Intel sales office or your distributor to obtain the latest specifications and before placing your product order. Copies of documents which have an ordering number and are referenced in this document, or other Intel literature may be obtained by calling 1-800-548-4725 or by visiting Intel's website at http://www.intel.com. ...
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... Peripheral Bus Interface Signal Timings ................................................ 59 2 4.4.4 I 4.4.5 UART Interface Signal Timings .............................................................. 61 4.4.6 Boundary Scan Test Signal Timings ...................................................... 62 4.5 AC Timing Waveforms ........................................................................................ 63 4.6 AC Test Conditions ............................................................................................. 67 Document Number: 273943-002 Intel® 80331 I/O Processor Datasheet ® 80331 I/O Processor ................................................................... 9 ® Core .............................................................................................. 11 C Interface Signal Timings................................................................... 61 November 2004 3 ...
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... Intel® 80331 I/O Processor Datasheet Figures ® 1 Intel 80331 I/O Processor I/O Processor Functional Block Diagram ................ 10 2 829-Ball FCBGA Package Diagram .................................................................... 34 ® 3 Intel 80331 I/O Processor Ballout (Bottom View).............................................. 35 ® 4 Intel 80331 I/O Processor Ballout - Left Side (Bottom View) ............................ 36 ® ...
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... DDR SDRAM Signal Timings ..............................................................................57 26 DDR-II SDRAM Signal Timings........................................................................... 58 27 Peripheral Bus Signal Timings ............................................................................ 59 28 PCI Signal Timings.............................................................................................. Signal Timings............................................................................................... 61 30 UART Signal Timings ..........................................................................................61 31 Boundary Scan Test Signal Timings ................................................................... Measurement Conditions ..............................................................................67 Document Number: 273943-002 Intel® 80331 I/O Processor Datasheet November 2004 5 ...
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... Intel® 80331 I/O Processor Datasheet Revision History Date Revision # November 2004 September 2003 6 002 Added D-0 text to Product Features and body text. Revised Ball Maps and Signal designations for intel® 80331 I/O processor design. Added ICC numbers to Table 22. 001 Initial Release. November 2004 Description ...
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... Intel Corporation assumes no responsibility for any errors which may appear in this document nor does it make a commitment to update the information contained herein. Intel retains the right to make changes to these specifications at any time, without notice. In particular, descriptions of features, timings, packaging, and pin-outs does not imply a commitment to implement them ...
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... I/O Processor Design Guide (273823), Intel Corporationl. ® 4. Intel 80331 I/O Processor Specification Update (273930), Intel Corporationl. 5. PCI-to-PCI Bridge Architecture Specification, Revision 1.1 - PCI Special Interest Group. 6. PCI Local Bus Specification, Revision 2.3 - PCI Special Interest Group. 7. PCI-X Addendum to the PCI Local Bus Specification, Revision 1.0a - PCI Special Interest Group ...
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... Two 16550 compatible UARTs with flow control (four pins). • Eight General Purpose Input Output (GPIO) ports integrated processor that addresses the needs of intelligent I/O applications and helps reduce intelligent I/O system costs. Document Number: 273943-002 ® 80331 I/O Processor core ...
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... Intel® 80331 I/O Processor Datasheet Introduction Figure functional block diagram of the 80331. ® Figure 1. Intel 80331 I/O Processor I/O Processor Functional Block Diagram Interrupt Controller & Timers Application Accelerator Primary PCI Bus 10 32/64-bit DDR ® Intel XScale Interface Core Memory ...
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... I2C Bus Interface • PCI-X to PCI-X Bridge with Primary and Secondary 133 MHz/64-bit PCI-X Interfaces The subsections that follow briefly overview each feature. Refer to the Intel Developer’s Manual for full technical descriptions. 2.1 Intel XScale The 80331 is based upon the Intel XScale frequency of 800 MHz ...
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... The ATU supports transactions between PCI address space and 80331 address space. Address translation for the ATU is controlled through programmable registers accessible from both the PCI interface and the Intel XScale 80331 Secondary PCI interface of the bridge. Upstream access to the Primary PCI interface is controlled by inverse decode with the address windows of the bridge ...
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... UART Units The 80331 includes two UART units. The UART units allow the Intel XScale master and slave device residing on the UART bus. The UART units use a serial bus consisting of a four-pin interface. The bus allows the 80331 to interface to other peripherals and microcontrollers. ...
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... Interrupt Controller Unit The Interrupt Controller Unit (ICU) aggregates interrupt sources both external and internal of the 80331 to the Intel XScale processing with direct interrupt service routine vector generation on a per source basis. Each source has programmability for masking, core processor interrupt input, and priority. ...
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... The pin is reset with S_RST#. Note that S_RST# is asserted when P_RST# is asserted. Rst(M) The pin is reset with M_RST#. Note that M_RST# is asserted when P_RST#is asserted or is asserted with software. Rst(T) The pin is reset with TRST#. Document Number: 273943-002 Intel® 80331 I/O Processor Datasheet Description November 2004 Package Information 15 ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 2. DDR SDRAM Signals Name Count M_CK[2:0] 3 M_CK[2:0]# 3 M_RST# 1 MA[13:0] 14 BA[1:0] 2 RAS# 1 CAS# 1 WE# 1 CS[1:0]# 2 CKE[1:0] 2 DQ[63:0] 64 CB[7:0] 8 DQS[8:0] 9 DM[8:0] 9 Total 120 16 Type O Memory Clocks are used to provide the positive differential clocks to the external SDRAM memory subsystem. ...
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... Table 4. MISC SDRAM Signals Name DDRCRES0 DDRSLWCRES DDRIMPCRES Total Document Number: 273943-002 Intel® 80331 I/O Processor Datasheet Count Type 9 I/O SDRAM Data Strobes carry the differential strobe signals in DDR-II mode, output in write mode and input in read mode for Sync(M) source synchronous data transfer. ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 5. Peripheral Bus Interface Signals Name Count A[22:16] AD[15:0] A[2:0] ALE POE# PWE# PCE[1]# PCE[0]# Total 18 Type 7 O Address Bus 22:16 carries a demultiplexed version of address bits A22:16. During address (T Rst(M) cycles, A22:16 represents the upper seven address bits for the current access ...
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... As an input, it indicates Rst(P) whether or not an agent has been selected. 1 I/O Primary PCI Bus System Error is driven for address parity errors on the PCI bus. OD Sync(P) Rst(P) November 2004 Intel® 80331 I/O Processor Datasheet Package Information Description 19 ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 6. Primary PCI Bus Signals (Sheet Name P_PERR# P_M66EN P_CLK P_RST# P_RCOMP Total NOTE: When the PCI bridge is disabled (BRG_EN = 0), all primary PCI interface signals become inactive, and the secondary interface becomes a primary PCI interface. ...
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... PCI bus interface output signals are three-stated. • Open drain signals such as S_SERR# are floated. S_RST# may be asynchronous to S_CLKIN when asserted or deasserted. Although asynchronous, deassertion must be ensured clean, bounce-free edge. November 2004 Intel® 80331 I/O Processor Datasheet Package Information Description 21 ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 7. Secondary PCI Bus Signals (Sheet Name Count S_PERR# S_CLKO[3:0] S_CLKOUT S_CLKIN/ 1 P_CLK S_M66EN S_REQ[3]#/ 1 P_IDSEL S_REQ[1]# 1 P_GNT# S_REQ[2,0]# S_GNT[3,2]# S_GNT[1]#/ 1 P_REQ# S_GNT[0]#/ 1 P_BMI S_PCIXCAP S_RCOMP Total NOTE: When the PCI Bridge is disabled (BRG_EN=0), all secondary PCI interface signals become primary interface signals ...
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... C Data is used for data transfer and arbitration of the I Clock provides synchronous operation of the I Data is used for data transfer and arbitration of the I 4 November 2004 Intel® 80331 I/O Processor Datasheet Package Information Description Description 2 C bus zero bus zero bus one bus one. 23 ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 10. UART Signals (Sheet Name GPIO[0]/ U0_RXD GPIO[1]/ U0_TXD GPIO[2]/ U0_CTS# GPIO[3]/ U0_RTS# 24 Count Type 1 I/O General Purpose I/O: These pins may be selected on a per pin basis as general purpose inputs or outputs. The default mode is a general purpose input ...
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... RTS# is automatically asserted by the autoflow circuitry when the Receive buffer exceeds its programmed threshold deasserted when enough bytes are removed from the buffer to lower the data level back to the threshold. 8 November 2004 Intel® 80331 I/O Processor Datasheet Package Information Description 25 ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 11. Test and Miscellaneous Signals Name TCK TDI TDO TRST# TMS N/C PU1 PU2 PWRDELAY Total 26 Count Type 1 I Test Clock provides clock input for IEEE 1149.1 Boundary Scan Testing (JTAG). State information and data are clocked into the device on the rising clock edge and data is clocked out on the falling clock edge ...
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... Functional Modes” on page 1 C Core Reset Mode is latched on the rising (deasserting) edge of P_RST# and determines when the Intel XScale until the processor reset bit is cleared in PCI configuration and status register Hold in reset. (Requires pull-down resistor not hold in reset. (Default mode) NOTE: Muxed onto signal AD[5], see for Functional Modes” ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 12. Reset Strap Signals (Sheet Name BRG_EN ARB_EN P_32BITPCI# PCIODT_EN Total 28 Count Type 1 Config Bridge Enable: BRG_EN latched at rising (deasserting) edge of P_RST# and determines if 80331 operates with PCI-to-PCI Bridge Disable Bridge, enable P_CLK input on S_CLKIN input. ...
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... Ground balls to be connected to a ground board plane. 4 GND Analog Ground balls need to be connected to the appropriate V filter, and not to board ground. CCPLL Note: There is no VSSA3 signal. November 2004 Intel® 80331 I/O Processor Datasheet Package Information Description supply ball for the phase lock CC15 CC15 plane. 29 ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 14. Pin Mode Behavior (Sheet Pin M_CK[2:0] M_CK[2:0]# M_RST# MA[13:0] BA[1:0] RAS# CAS# WE# CS[1:0]# CKE[1:0] DQ[63:32] DQ[31:0] CB[7:0] DQS[8] DQS[7:4] DQS[3:0] DQS[8]# DQS[7:4]# DQS[3:0]# DM[8] DM[7:4] DM[3:0] DDR_VREF ODT[1:0] (2) DDRRES[2:1] DDRCRES0 DDRSLWCRES DDRIMPCRES ...
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... P_RST# P_PERR# P_M66EN S_AD[63:32] S_AD[31:0] S_PAR S_PAR64 S_C/BE[3:0]# S_C/BE[7:4]# S_REQ64# S_ACK64# S_FRAME# S_IRDY# S_TRDY# S_STOP# S_DEVSEL# S_SERR# S_RST# S_PERR# S_LOCK# S_CLKO[3:0] S_CLKOUT Document Number: 273943-002 Intel® 80331 I/O Processor Datasheet Reset Norm Reset Norm Lind Lind Lind Lind nobrg nobrg ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 14. Pin Mode Behavior (Sheet Pin S_CLKIN S_M66EN S_REQ[3]#/ P_IDSEL S_REQ[1]#/ P_GNT# S_REQ[2,0]# S_GNT[3,2]#, S_GNT[1]#/ P_REQ# S_GNT[0]#/ P_BMI S_PCIXCAP P_RCOMP S_RCOMP P_INT[D:A]# S_INT[D:A]# HPI# SCL0, SCD0, SCL1, SCD1 GPIO[3:0]/ U0_RTS#, U0_CTS#, U0_TXD, U0_RXD, ...
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... Pin Multiplexing for Functional Modes Pin A[20] AD[6] AD[5] AD[4] AD[3] AD[2] AD[1] AD[0] A[2] A[1] A[0] S_REQ[3]# S_REQ[1]# S_GNT[1]# S_GNT[0]# S_CLKIN Document Number: 273943-002 Intel® 80331 I/O Processor Datasheet Bridge Disabled - - - - - - - - - - - P_IDSEL P_GNT# P_REQ# P_BMI P_CLK November 2004 Package Information ...
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... Intel® 80331 I/O Processor Datasheet Package Information Figure 2. 829-Ball FCBGA Package Diagram F2 Top View Seating Plane Table 16. FC-style, H-PBGA Package Dimensions Symbol NOTE: Measurement in millimeters Pin #1 Die Corner Laser Mark Side View 829-Pin BGA Minimum 2.392 0.50 0.742 1.15 37.45 37 ...
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... Figure 3. Intel 80331 I/O Processor Ballout (Bottom View JTAG Document Number: 273943-002 DDRII/SDRAM VCC/VSS Primary PCI-X Bus November 2004 Intel® 80331 I/O Processor Datasheet Package Information GPIO PBI Secondary PCI-X Bus B1210- ...
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... Intel® 80331 I/O Processor Datasheet Package Information ® Figure 4. Intel 80331 I/O Processor Ballout - Left Side (Bottom View VSS AG DQ6 AF DM0 AE DQ5 AD DDR_ AC VREF AB N/C AA N/C Y VCC15 PWR W DELAY P_ V RCOMP INTD C/BE4# C/BE5# N AD63 PAR64 P_ P AD60 P_ N AD59 ...
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... N/C N/C VSS VSS VSS AD30 AD26 GNT1 VSS N/C N/C N/C AD31 AD29 GNT0# AD24 November 2004 Intel® 80331 I/O Processor Datasheet Package Information DQS6# DQS6 VSS VSS DQ54 DQ55 VSS NB AH VSS DM6 DQ50 DQ51 DQ60 VSS AG VCC ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 17. 829-Lead Package - Alphabetical Ball Listings (Sheet Ball P_AD16 A5 P_AD18 A6 P_AD21 A7 P_C/BE3# A8 P_AD26 A9 P_AD29 A10 A11 A12 A13 A14 A15 A16 A17 A18 A19 A20 A21 S_AD31 A22 S_AD29 A23 S_GNT0# A24 S_AD24 ...
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... G24 S_CLKO1 N/C G25 S_CLKOUT N/C G26 VSS G27 S_CLKIN N/C G28 N/C G29 S_PERR# VSS H1 P_AD0 S_AD13 H2 November 2004 Intel® 80331 I/O Processor Datasheet Package Information Ball Signal H3 P_AD1 H4 P_AD2 H5 VCC33 H6 P_ACK64# VSS H7 N/C H8 N/C H9 N/C VSS H10 P_TRDY# ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 17. 829-Lead Package - Alphabetical Ball Listings (Sheet Ball J15 J16 J17 J18 J19 J20 J21 J22 S_AD47 J23 S_AD46 J24 J25 S_AD45 J26 S_AD44 J27 J28 S_ACK64# J29 S_REQ64# K1 P_AD50 K2 K3 P_IDSEL K4 K5 ...
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... T10 VSS T11 VCC15 S_AD56 T12 P_AD63 T13 VCC15 P_PAR64 T14 VCC33 T15 VCC15 N/C T16 November 2004 Intel® 80331 I/O Processor Datasheet Package Information Ball Signal T17 VCC15 T18 VSS T19 VCC15 T20 VSS VSS T21 AD10 T22 AD6 ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 17. 829-Lead Package - Alphabetical Ball Listings (Sheet Ball U29 S_AD48 V1 P_RCOMP V2 P_INTD P_INTC# V5 P_INTB V10 V11 V12 V13 V14 V15 V16 V17 V18 V19 V20 V21 V22 V23 V24 V25 V26 V27 V28 ...
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... AD23 MA2 AD24 VCC25/18 MA0 AD25 CB5 AD26 CB4 AD27 CB3 AD28 VSS AD29 MA10 AE1 November 2004 Intel® 80331 I/O Processor Datasheet Package Information Ball Signal RAS# AE2 VSS AE3 DQS0# CAS# AE4 DQS0 ODT0 AE5 VSS VSS AE6 ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 17. 829-Lead Package - Alphabetical Ball Listings (Sheet Ball AF14 AF15 AF16 AF17 VCC25/18 AF18 AF19 AF20 VCC25/18 AF21 AF22 VCC25/18 AF23 AF24 AF25 AF26 VCC25/18 AF27 AF28 AF29 AG1 AG2 AG3 AG4 AG5 ...
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... AD10 AD11 AD12 AD13 AD14 AD15 AD2 AD3 AD4 AD5 AD6 AD7 AD8 AD9 ALE BA0 BA1 Document Number: 273943-002 Intel® 80331 I/O Processor Datasheet Ball Signal Ball A1 CAS# AC21 A2 CB0 AE15 A28 CB1 AF15 A29 CB2 AD17 AH1 CB3 ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 18. 829-Lead Package - Alphabetical Signal Listings (Sheet Signal DQ58 DQ59 DQ6 DQ60 DQ61 DQ62 DQ63 DQ7 DQ8 DQ9 DQS0 DQS0# DQS1 DQS1# DQS2 DQS2# DQS3 DQS3# DQS4 DQS4# DQS5 DQS5# DQS6 DQS6# DQS7 ...
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... P_AD28 P_AD29 P_AD3 P_AD30 P_AD31 P_AD32 P_AD33 P_AD34 P_AD35 P_AD36 P_AD37 P_AD38 P_AD39 P_AD4 P_AD40 P_AD41 P_AD42 P_AD43 Document Number: 273943-002 Intel® 80331 I/O Processor Datasheet Ball Signal Ball AB20 P_AD45 R5 H6 P_AD46 R7 H1 P_AD47 R8 H3 P_AD48 J2 D1 P_AD49 J1 D2 ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 18. 829-Lead Package - Alphabetical Signal Listings (Sheet Signal S_AD27 S_AD28 S_AD29 S_AD3 S_AD30 S_AD31 S_AD32 S_AD33 S_AD34 S_AD35 S_AD36 S_AD37 S_AD38 S_AD39 S_AD4 S_AD40 S_AD41 S_AD42 S_AD43 S_AD44 S_AD45 S_AD46 S_AD47 S_AD48 S_AD49 ...
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... VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC15 VCC25/18 VCC25/18 VCC25/18 VCC25/18 VCC25/18 Document Number: 273943-002 Intel® 80331 I/O Processor Datasheet Ball Signal Ball N10 VCC25/18 AA20 N12 VCC25/18 AB11 N14 VCC25/18 AB13 N16 VCC25/18 AB15 N18 ...
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... Intel® 80331 I/O Processor Datasheet Package Information Table 18. 829-Lead Package - Alphabetical Signal Listings (Sheet Signal VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS ...
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... VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS VSS Document Number: 273943-002 Intel® 80331 I/O Processor Datasheet Ball Signal Ball J6 VSS P2 J9 VSS P20 K12 VSS P25 K14 VSS P28 K15 VSS ...
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... Intel® 80331 I/O Processor Datasheet Package Information 3.2 Package Thermal Specifications ® See Intel 80331 I/O Processor Thermal Design Guidelines Application Note (273980). 52 November 2004 Document Number: 273943-002 ...
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... V Pin Requirements CCPLL The V CCPLL[1-5] connected to the appropriate VSSA ball. See the Intel specific recommendations. NOTE: There are no VCCPLL3 or VSSA3 signals. Document Number: 273943-002 NOTE: This data sheet contains information on Maximum Rating –55° +125°C 0°C to +105°C wrt. V – ...
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... Intel® 80331 I/O Processor Datasheet Electrical Specifications 4.3 Targeted DC Specifications Table 21. DC Characteristics Symbol Parameter V Input Low Voltage (DDR SDRAM) IL1 V Input High Voltage (DDR SDRAM) IH1 V Input Low Voltage (DDR-II SDRAM) IL2 V Input High Voltage (DDR-II SDRAM) IH2 V Input Low Voltage (Misc.) ...
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... Supply) I Active Power Supply Current - DDR-II CC18 (Power Supply) I Active Power Supply Current - IOP/Bridge core CC15 (Power Supply) I Active Power Supply Current - Intel XScale CC13 (Power Supply) core I Active Thermal Current - PCI-X interfaces CC33 (Thermal) I Active Thermal Current - DDR CC25 ...
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... Intel® 80331 I/O Processor Datasheet Electrical Specifications 4.4 Targeted AC Specifications 4.4.1 Clock Signal Timings Table 23. PCI Clock Timings Symbol Parameter T PCI clock Frequency F1 T PCI clock Cycle Time C1 T PCI clock High Time CH1 T PCI clock Low Time CL1 T PCI clock Slew Rate ...
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... Figure 12 “DDR SDRAM Read Timings” on page 6. See Figure 13 “Write PreAmble/PostAmble Durations” on page 7. See Figure 15 “AC Test Load for DDR SDRAM Signals” on page 8. Address/Command pin group; RAS# Document Number: 273943-002 Intel® 80331 I/O Processor Datasheet Parameter Minimum (nominal) (nominal) 63. 64. ...
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... Intel® 80331 I/O Processor Datasheet Electrical Specifications Table 26. DDR-II SDRAM Signal Timings Symbol T DQ, CB and DM write output valid time before DQS crossing. VB1 T DQ, CB and DM write output valid time after DQS crossing. VA1 T Address and Command write output valid before M_CK rising ...
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... See Table 32, AC Measurement Conditions. 5. All timing referenced to M_CK is for functional testing, for the cases where M_CK * N = IBCLK. 6. PBI Clock is internal only; 66 MHz with 266 MHz internal bus. Document Number: 273943-002 Intel® 80331 I/O Processor Datasheet Parameter 63. 64. November 2004 ...
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... Intel® 80331 I/O Processor Datasheet Electrical Specifications Table 28. PCI Signal Timings Symbol Parameter T Clock to Output Valid OV1 Delay for bused signals T Clock to Output Valid OV2 Delay for point to point signals T Clock to Output Float OF Delay T Input Setup to clock IS1 for bused signals ...
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... Ux_CTS hold time (to M_CK rising edge). CTH1 T Ux_RTS setup time (to M_CK rising edge). RTS1 T Ux_RTS hold time (to M_CK rising edge). RTH1 1. See Figure 10 “UART Transmitter Receiver Timing” on page Document Number: 273943-002 Intel® 80331 I/O Processor Datasheet Std. Mode Parameter Min. Max 0 100 4 ...
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... Intel® 80331 I/O Processor Datasheet Electrical Specifications 4.4.6 Boundary Scan Test Signal Timings Table 31. Boundary Scan Test Signal Timings Symbol T TCK Frequency BSF T TCK High Time BSCH T TCK Low Time BSCL T TCK Rise Time BSCR T TCK Fall Time BSCF T Input Setup to TCK — TDI, ...
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... AC Timing Waveforms Figure 6. Clock Timing Measurement Waveforms Figure 7. Output Timing Measurement Waveforms Document Number: 273943-002 Intel® 80331 I/O Processor Datasheet ih(min) V il(max CLK V test T OV OUTPUT DELAY FALL T OV OUTPUT DELAY RISE T OF OUTPUT FLOAT November 2004 Electrical Specifications ...
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... Intel® 80331 I/O Processor Datasheet Electrical Specifications Figure 8. Input Timing Measurement Waveforms INPUT 2 Figure 9. I C/SMBus Interface Signal Timings SDA T BUF SCL Stop Figure 10. UART Transmitter Receiver Timing M_CK Ux_TXD Ux_RXD 64 CLK V test Valid test T LOW HDSTA HDDAT HIGH SUDAT ...
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... Figure 11. DDR SDRAM Write Timings ADDR/CTRL CS[1:0]# M_CK DQS DQS# DQ Figure 12. DDR SDRAM Read Timings DQS DQ Document Number: 273943-002 Intel® 80331 I/O Processor Datasheet T VA3 T VB3 T VA5 T VB5 T VA1 T VB1 T VB6 November 2004 Electrical Specifications T VB4 T VA4 65 ...
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... Intel® 80331 I/O Processor Datasheet Electrical Specifications Figure 13. Write PreAmble/PostAmble Durations DQS DQS 66 T VB6 November 2004 T VA6 Document Number: 273943-002 ...
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... Output 50pF 1.25V 25Ω 25Ω Output Rising Edge AC Test Load Output 25Ω November 2004 Intel® 80331 I/O Processor Datasheet Electrical Specifications DDR-II PBI 1.15 2.0 0.2 0.8 0.90 1.5 0.90 1.5 0.90 1.5 0.97 1.2 1.0 1 ...
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... Intel® 80331 I/O Processor Datasheet Electrical Specifications Figure 17. PCI/PCI-X T OV(max) Figure 18. PCI/PCI-X T OV(min) 68 Falling Edge AC Test Load V CC33 25Ω Output 10pF AC Test Load V CC33 1KΩ Output 1KΩ 10pF November 2004 Test Point Test Point Document Number: 273943-002 ...