NQ80331M667SL7NM Intel, NQ80331M667SL7NM Datasheet - Page 25

• Manufacturer Part Number: NQ80331M667SL7NM
• Description: IC I/O PROCESSOR 733MHZ 829-BGA
• Manufacturer: Intel

Specifications of NQ80331M667SL7NM

• Rohs Status: RoHS non-compliant
• Processor Type: I/O
• Features: XScale Core
• Speed: 733MHz
• Voltage: 1.35V
• Mounting Type: Surface Mount
• Package / Case: 829-BGA
• Other names: 862506

Document Number: 273943-002
Table 10.
UART Signals (Sheet 2 of 2)
U1_CTS#
U1_RTS#
GPIO[4]/
U1_RXD
GPIO[5]/
GPIO[6]/
GPIO[7]/
U1_TXD
Name
Total
Count
1
1
1
1
8
Type
I/O
I/O
I/O
I/O
November 2004
General Purpose I/O: These pins may be selected on a per pin
basis as general purpose inputs or outputs. The default mode is a
general purpose input.
Serial Input: Serial data input from device pin to receive shift register.
General Purpose I/O: These pins may be selected on a per pin
basis as general purpose inputs or outputs. The default mode is a
general purpose input.
Serial Output: Composite serial data output to the communications
link-peripheral, modem, or data set. The TXD signal is set to the
MARKING (logic 1) state upon a Reset operation.
General Purpose I/O: These pins may be selected on a per pin
basis as general purpose inputs or outputs. The default mode is a
general purpose input.
Clear To Send: When low, this pin indicates that the receiving UART is
ready to receive data. When the receiving UART deasserts CTS# high,
the transmitting UART should stop transmission to prevent overflow of
the receiving UARTs buffer. The CTS# signal is a modem-status input
whose condition may be tested by the host processor or by the UART
when in Autoflow mode as described below:
Non-Autoflow Mode:
When not in Autoflow mode, bit 4 (CTS) of the Modem Status
register (MSR) indicates the state of CTS#. Bit 4 is the complement
of the CTS# signal. Bit 0 (DCTS) of the Modem Status register
indicates whether the CTS# input has changed state since the
previous reading of the Modem Status register. CTS# has no effect
on the transmitter. The user may program the UART to interrupt the
processor when DCTS changes state. The programmer may then
stall the outgoing data stream by starving the transmit FIFO or
disabling the UART with the IER register.
NOTE: When UART transmission is stalled by disabling the UART,
Autoflow Mode:
NOTE: In Autoflow mode, the UART Transmit circuitry will check
General Purpose I/O: These pins may be selected on a per pin
basis as general purpose inputs or outputs. The default mode is a
general purpose input.
Request To Send: When low, this informs the remote device that
the UART is ready to receive data. A reset operation sets this signal
to its Inactive (high) state. LOOP mode operation holds this signal in
its Inactive state.
Non-Autoflow Mode:
The RTS# output signal may be asserted by setting bit 1 (RTS) of
the Modem Control register to a 1. The RTS bit is the complement
of the RTS# signal.
Autoflow Mode:
RTS# is automatically asserted by the autoflow circuitry when the
Receive buffer exceeds its programmed threshold. It is deasserted
when enough bytes are removed from the buffer to lower the data
level back to the threshold.
the user may not receive an MSR interrupt when CTS#
reasserts. This occurs because disabling the UART also
disables interrupts. As a workaround, the user may use Auto
CTS in Autoflow Mode, or program the CTS# pin to interrupt.
the state of CTS# before transmitting each byte. When
CTS# is high, no data is transmitted.
Intel® 80331 I/O Processor Datasheet
Description
Package Information
25