NQ80331M667SL7NM Intel, NQ80331M667SL7NM Datasheet - Page 19

• Manufacturer Part Number: NQ80331M667SL7NM
• Description: IC I/O PROCESSOR 733MHZ 829-BGA
• Manufacturer: Intel

Specifications of NQ80331M667SL7NM

• Rohs Status: RoHS non-compliant
• Processor Type: I/O
• Features: XScale Core
• Speed: 733MHz
• Voltage: 1.35V
• Mounting Type: Surface Mount
• Package / Case: 829-BGA
• Other names: 862506

Document Number: 273943-002
Table 6.
Primary PCI Bus Signals (Sheet 1 of 2)
P_C/BE[7:0]#
P_AD[63:32]
P_DEVSEL#
P_AD[31:0]
P_FRAME#
P_REQ64#
P_ACK64#
P_TRDY#
P_STOP#
P_SERR#
P_PAR64
P_IDSEL
P_IRDY#
P_REQ#
P_GNT#
P_PAR
Name
Count
32
32
1
1
8
1
1
1
1
1
1
1
1
1
1
1
Sync(P)
Sync(P)
Sync(P)
Sync(P)
Sync(P)
Sync(P)
Sync(P)
Sync(P)
Sync(P)
Sync(P)
Sync(P)
Sync(P)
Sync(P)
Sync(P)
Sync(P)
Sync(P)
Rst(P)
Rst(P)
Rst(P)
Rst(P)
Rst(P)
Rst(P)
Rst(P)
Rst(P)
Rst(P)
Rst(P)
Rst(P)
Rst(P)
Rst(P)
Rst(P)
Type
November 2004
OD
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
I/O
O
I
I
Primary PCI Address/Data is the multiplexed PCI address and
lower 32 bits of the data bus.
Primary PCI Address/Data is the upper 32 bits of the PCI data bus
driven during the data phase.
Primary PCI Bus Parity is even parity across P_AD[31:0] and
P_C/BE[3:0]#.
Primary PCI Bus Upper DWORD Parity is even parity across
P_AD[63:32] and P_C/BE[7:4]#
Primary PCI Bus Command and Byte Enables are multiplexed
on the same PCI pins. During the address phase, they define the
bus command. During the data phase, they are used as byte
enables for P_AD[63:0].
Primary PCI Bus Request indicates to the PCI bus arbiter that the
I/O processor desires use of the PCI bus.
Primary PCI Bus Request 64-Bit Transfer indicates the attempt
of a 64-bit transaction on the PCI bus. When the target is 64-bit
capable, the target acknowledges the attempt with the assertion of
P_ACK64#.
Primary PCI Bus Initialization Device Select is used to select the
80331 during a Configuration Read or Write command on the PCI
bus.
Primary PCI Bus Grant indicates that access to the PCI bus has
been granted.
Primary PCI Bus Acknowledge 64-Bit Transfer indicates that the
device has positively decoded its address as the target of the
current access and the target is willing to transfer data using the full
64-bit data bus.
Primary PCI Bus Cycle Frame is asserted to indicate the
beginning and duration of an access.
Primary PCI Bus Initiator Ready indicates the initiating agent’s
ability to complete the current data phase of the transaction. During a
write, it indicates that valid data is present on the Address/Data bus.
During a read, it indicates the processor is ready to accept the data.
Primary PCI Bus Target Ready indicates the target agent’s ability
to complete the current data phase of the transaction. During a read,
it indicates that valid data is present on the Address/Data bus. During
a write, it indicates the target is ready to accept the data.
Primary PCI Bus Stop indicates a request to stop the current
transaction on the PCI bus.
Primary PCI Bus Device Select is driven by a target agent that
has successfully decoded the address. As an input, it indicates
whether or not an agent has been selected.
Primary PCI Bus System Error is driven for address parity errors
on the PCI bus.
Intel® 80331 I/O Processor Datasheet
Description
Package Information
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