MC68020RC20E Freescale Semiconductor, MC68020RC20E Datasheet - Page 159

• Manufacturer Part Number: MC68020RC20E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

During coprocessor instruction execution, the MC68020/EC020 executes CPU space bus
cycles to access the CIR set. The MC68020/EC020 asserts FC2–FC0, identifying a CPU
space bus cycle. The CIR set is mapped into CPU space in the same manner that a
peripheral interface register set is generally mapped into data space. The information
encoded on FC2–FC0 and the address bus of the MC68020/EC020 during a coprocessor
access is used to generate the chip select signal for the coprocessor being accessed.
Other address lines select a register within the interface set. The information encoded on
the function code and address lines of the MC68020/EC020 during a coprocessor access
is illustrated in Figure 7-3.
Signals A19–A16 of the MC68020/EC020 address bus specify the CPU space cycle type
for a CPU space bus cycle. The types of CPU space cycles currently defined for the
MC68020/EC020 are interrupt acknowledge, breakpoint acknowledge, module support
operations, and coprocessor access cycles. CPU space type $2 (A19–A16 = 0010)
specifies a coprocessor access cycle.
A15–A13 specify the CpID code for the coprocessor being accessed. This code is
transferred from bits 11–9 of the coprocessor instruction operation word (refer to Figure
7-1) to the address bus during each coprocessor access. Thus, decoding the
MC68020/EC020 FC2–FC0 and A19–A13 signals provides a unique chip select signal for
a given coprocessor. The FC2–FC0 and A19–A16 signals indicate a coprocessor access;
A15–A13 indicate which of the possible eight coprocessors (000–111) is being accessed.
Bits A31–A20 and A12–A5 of the MC68020 address bus and bits A23–A20 and A12–A5
of the MC68EC020 address bus are always zero during a coprocessor access.
7.1.4.3 COPROCESSOR INTERFACE REGISTER SELECTION. Figure 7-4 shows that
the value on the MC68020/EC020 address bus during a coprocessor access addresses a
unique region of the main processor's CPU address space. Signals A4–A0 of the
MC68020/EC020 address bus select the CIR being accessed. The register map for the
M68000 coprocessor interface is shown in Figure 7-5. The individual registers are
described in detail in 7.3 Coprocessor Interface Register Set.
7-6
FUNCTION
2
1
CODE
1
0
1
31
Figure 7-3. MC68020/EC020 CPU Space Address Encodings
0
0
0
0
0
Freescale Semiconductor, Inc.
0
For More Information On This Product,
0
0
0
M68020 USER’S MANUAL
0
Go to: www.freescale.com
0
20
0
19
0
CPU SPACE
TYPE FIELD
0
1
ADDRESS
16
0
BUS
15
CpID
13
12
0
0
0
0
0
0
0 0
5
4
MOTOROLA
CIR
0