MC68020RC20E Freescale Semiconductor, MC68020RC20E Datasheet - Page 197

• Manufacturer Part Number: MC68020RC20E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

The transfer multiple coprocessor registers primitive uses the CA, PC, and DR bits as
described in 7.4.2 Coprocessor Response Primitive General Format.
The length field of the primitive format indicates the length in bytes of each operand
transferred. The operand length must be an even number of bytes; odd length operands
cause the MC68020/EC020 to initiate protocol violation exception processing (refer to
7.5.2.1 Protocol Violations).
When the main processor reads this primitive, it calculates the effective address specified
in the coprocessor instruction. The scanPC should be pointing to the first of any necessary
effective address extension words when this primitive is read from the response CIR; the
scanPC is incremented by two for each extension word referenced during the effective
address calculation. For transfers from the effective address to the coprocessor (DR = 0),
the control addressing modes and the postincrement addressing mode are valid. For
transfers from the coprocessor to the effective address (DR = 1), the control alterable and
predecrement addressing modes are valid. Invalid addressing modes cause the
MC68020/EC020 to abort the instruction by writing an abort mask to the control CIR (refer
to 7.3.2 Control CIR) and to initiate F-line emulator exception processing (refer to 7.5.2.2
F-Line Emulator Exceptions).
After performing the effective address calculation, the MC68020/EC020 reads a 16-bit
register select mask from the register select CIR. The coprocessor uses the register select
mask to specify the number of operands to transfer; the MC68020/EC020 counts the
number of ones in the register select mask to determine the number of operands. The
order of the ones in the register select mask is not relevant to the operation of the main
processor. As many as 16 operands can be transferred by the main processor in response
to this primitive. The total number of bytes transferred is the product of the number of
operands transferred and the length of each operand specified in the length field of the
primitive format.
If DR = 1, the main processor reads the number of operands specified in the register
select mask from the operand CIR and writes these operands to the effective address
specified in the instruction using long-word transfers whenever possible. If DR = 0, the
main processor reads the number of operands specified in the register select mask from
the effective address and writes them to the operand CIR.
For the control addressing modes, the operands are transferred to or from memory using
ascending addresses. For the postincrement addressing mode, the operands are read
from memory with ascending addresses also, and the address register used is
incremented by the size of an operand after each operand is transferred. The address
register used with the (An)+ addressing mode is incremented by the total number of bytes
transferred during the primitive execution.
7-44
Figure 7-37. Transfer Multiple Coprocessor Registers Primitive Format
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CA
PC
14
DR
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Freescale Semiconductor, Inc.
For More Information On This Product,
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M68020 USER’S MANUAL
Go to: www.freescale.com
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LENGTH
MOTOROLA
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