MC68020RC20E Freescale Semiconductor, MC68020RC20E Datasheet - Page 48

• Manufacturer Part Number: MC68020RC20E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

Freescale Semiconductor, Inc.
SECTION 5
BUS OPERATION
This section provides a functional description of the bus, the signals that control it, and the
bus cycles provided for data transfer operations. It also describes the error and halt
conditions, bus arbitration, and reset operation. Operation of the bus is the same whether
the processor or an external device is the bus master; the names and descriptions of bus
cycles are from the point of view of the bus master. For exact timing specifications, refer to
Section 10 Electrical Characteristics.
The MC68020/EC020 architecture supports byte, word, and long-word operands, allowing
access to 8-, 16-, and 32-bit data ports through the use of asynchronous cycles controlled
by the DSACK1 and DSACK0 input signals.
The MC68020/EC020 allows byte, word, and long-word operands to be located in memory
on any byte boundary. For a misaligned transfer, more than one bus cycle may be
required to complete the transfer, regardless of port size. For a port less than 32 bits wide,
multiple bus cycles may be required for an operand transfer due to either misalignment or
a port width smaller than the operand size. Instruction words and their associated
extension words must be aligned on word boundaries. The user should be aware that
misalignment of word or long-word operands can cause the MC68020/EC020 to perform
multiple bus cycles for the operand transfer; therefore, processor performance is
optimized if word and long-word memory operands are aligned on word or long-word
boundaries, respectively.
5.1 BUS TRANSFER SIGNALS
The bus transfers information between the MC68020/EC020 and an external memory,
coprocessor, or peripheral device. External devices can accept or provide 8 bits, 16 bits,
or 32 bits in parallel and must follow the handshake protocol described in this section. The
maximum number of bits accepted or provided during a bus transfer is defined as the port
width. The MC68020/EC020 contains an address bus that specifies the address for the
transfer and a data bus that transfers the data. Control signals indicate the beginning of
the cycle, the address space and size of the transfer, and the type of cycle. The selected
device then controls the length of the cycle with the signal(s) used to terminate the cycle.
Strobe signals, one for the address bus and another for the data bus, indicate the validity
of the address and provide timing information for the data.
The bus operates in an asynchronous mode for any port width. The bus and control input
signals are internally synchronized to the MC68020/EC020 clock, introducing a delay. This
delay is the time period required for the MC68020/EC020 to sample an input signal,
synchronize the input to the internal clocks of the processor, and determine whether the
MOTOROLA
M68020 USER’S MANUAL
5- 1
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