MC68020RC20E Freescale Semiconductor, MC68020RC20E Datasheet - Page 199

• Manufacturer Part Number: MC68020RC20E
• Description: IC MICROPROCESSOR 32BIT 114-PGA
• Manufacturer: Freescale Semiconductor

Specifications of MC68020RC20E

• Processor Type: M680x0 32-Bit
• Speed: 20MHz
• Voltage: 5V
• Mounting Type: Surface Mount
• Package / Case: 114-PGA
• Family Name: M68000
• Device Core: ColdFire
• Device Core Size: 32b
• Frequency (max): 20MHz
• Instruction Set Architecture: RISC
• Supply Voltage 1 (typ): 5V
• Operating Supply Voltage (max): 5.25V
• Operating Supply Voltage (min): 4.75V
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Mounting: Through Hole
• Pin Count: 114
• Package Type: PGA
• Lead Free Status / RoHS Status: Contains lead / RoHS Compliant
• Features: -
• Lead Free Status / Rohs Status: Compliant

If SP = 0 and DR = 0, the main processor writes the 16-bit SR value to the operand CIR. If
SP = 0 and DR = 1, the main processor reads a 16-bit value from the operand CIR into the
main processor SR.
If SP = 1 and DR = 0, the main processor writes the long-word value in the scanPC to the
instruction address CIR and then writes the SR value to the operand CIR. If SP = 1 and
DR = 1, the main processor reads a 16-bit value from the operand CIR into the SR and
then reads a long-word value from the instruction address CIR into the scanPC.
With this primitive, a general category instruction can change the main processor program
flow by placing a new value in the SR, in the scanPC, or new values in both the SR and
the scanPC. By accessing the SR, the coprocessor can determine and manipulate the
main processor condition codes, supervisor status, trace modes, selection of the active
stack, and interrupt mask level.
The MC68020/EC020 discards any instruction words that have been prefetched beyond
the current scanPC location when this primitive is issued with DR = 1 (transfer to main
processor). The MC68020/EC020 then refills the instruction pipe from the scanPC
address in the address space indicated by the S-bit of the SR.
If the MC68020/EC020 is operating in the trace on change of flow mode (T1, T0 in the SR
= 01) when the coprocessor instruction begins to execute and if this primitive is issued
with DR = 1 (from coprocessor to main processor), the MC68020/EC020 prepares to take
a trace exception. The trace exception occurs when the coprocessor signals that it has
completed all processing associated with the instruction. Changes in the trace modes due
to the transfer of the SR to the main processor take effect on execution of the next
instruction.
7.4.18 Take Preinstruction Exception Primitive
The take preinstruction exception primitive initiates exception processing using a
coprocessor-supplied exception vector number and the preinstruction exception stack
frame format. This primitive applies to general and conditional category instructions.
Figure 7-40 shows the format of the take preinstruction exception primitive.
The take preinstruction exception primitive uses the PC bit as described in 7.4.2
Coprocessor Response Primitive General Format. The vector number field contains
the exception vector number used by the main processor to initiate exception processing.
When the main processor receives this primitive, it acknowledges the coprocessor
exception request by writing an exception acknowledge mask to the control CIR (refer to
7.3.2 Control CIR). The MC68020/EC020 then proceeds with exception processing as
7-46
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Figure 7-40. Take Preinstruction Exception Primitive Format
PC
14
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Freescale Semiconductor, Inc.
For More Information On This Product,
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1
10
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M68020 USER’S MANUAL
Go to: www.freescale.com
9
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7
VECTOR NUMBER
MOTOROLA
0