IDT92HD75B1X3NLGXYAX8 IDT, Integrated Device Technology Inc, IDT92HD75B1X3NLGXYAX8 Datasheet - Page 18
IDT92HD75B1X3NLGXYAX8
Manufacturer Part Number
IDT92HD75B1X3NLGXYAX8
Description
IC AUDIO CODEC HD 4CH 32-VFQFPN
Manufacturer
IDT, Integrated Device Technology Inc
Type
Audio Codec, HDr
Datasheet
1.IDT92HD75B1X3NLGXYAX8.pdf
(214 pages)
Specifications of IDT92HD75B1X3NLGXYAX8
Resolution (bits)
24 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
No
S/n Ratio, Adcs / Dacs (db) Typ
86 / 95
Dynamic Range, Adcs / Dacs (db) Typ
86 / 93
Voltage - Supply, Analog
3.14 V ~ 3.47 V; 3.8 V ~ 4.2 V; 4.28 V ~ 4.73 V; 4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.14 V ~ 3.47 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-VFQFN, 32-VFQFPN
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
92HD75B1X3NLGXYAX8
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4-CHANNEL HD AUDIO CODECS OPTIMIZED FOR LOW POWER
D0-D3
92HD75B
4-CHANNEL HD AUDIO CODECS OPTIMIZED FOR LOW POWER
AFG Power
State
1.4.12. Digital Microphone Support
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
Asserted (Low)
The digital microphone interface permits connection of a digital microphone(s) to the CODEC via the
DMIC0, DMIC1 (48QFN package only), and DMIC_CLK 3-pin interface. The DMIC0 and DMIC1 sig-
nals are inputs that carry individual channels of digital Mic data to the ADC. In the event that a single
microphone is used, the data is ported to both ADC channels.
The DMIC_CLK output is controllable from 4.704Mhz, 3.528Mhz, 2.352Mhz, 1.176Mhz and is syn-
chronous to the 24Mhz internal clock. The default frequency is 2.352Mhz.
92HD75B supports the following digital microphone configurations:
RESET#
GPIO Enable
Disabled
Disabled
Disabled
Enabled
-
Table 6. EAPD Behavior
Output Enable
18
Disabled
Disabled
Enabled
-
-
EAPD Power
D2-D3
D0-D1
State
-
-
-
92HD75B
output (internal pull-down enabled)
Active - Pin drives the value of the
Hi-Z (internal pull-down enabled)
Hi-Z (internal pull-down enabled)
Active - Pin Drives SPDIFOut0/1
retained until the rising edge of
otherwise the previous state is
configuration (internal pull-up
EAPD bit (internal pull-down
immediately after power on,
Active - Pin reflects GPIO0
Pin Behavior
RESET#
enabled)
enabled)
PC AUDIO
V 1.0 01-09
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