IDTSTAC9753AXTAED1XR IDT, Integrated Device Technology Inc, IDTSTAC9753AXTAED1XR Datasheet - Page 61
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IDTSTAC9753AXTAED1XR
Manufacturer Part Number
IDTSTAC9753AXTAED1XR
Description
IC CODEC AC'97 MIC/JACK 48-QFP
Manufacturer
IDT, Integrated Device Technology Inc
Type
Audio Codec '97r
Datasheet
1.IDTSTAC9752AXNAED1XR.pdf
(106 pages)
Specifications of IDTSTAC9753AXTAED1XR
Resolution (bits)
20 b
Number Of Adcs / Dacs
2 / 2
Sigma Delta
Yes
S/n Ratio, Adcs / Dacs (db) Typ
85 / 92
Voltage - Supply, Analog
3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
Voltage - Supply, Digital
3.14 V ~ 3.47 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
48-QFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
STAC9753AXTAED1XR
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
IDTSTAC9753AXTAED1XR
Manufacturer:
IDT, Integrated Device Technology Inc
Quantity:
10 000
IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
7.1.17.
Bit(s) Reset Value
14-13
15
12
11
D15
D7
I4
Audio Interrupt and Paging (24h)
Default: 0000h
0
0
0
0
D14
D6
I3
Read / Write
Read / Write
Read / Write
Read Only
Reserved
Access
D13
D5
I2
Name
I3-I2
I4
I1
I0
D12
61
D4
0 = Interrupt is clear
1 = interrupt is set
Interrupt event is cleared by writing a 1 to this bit.
The interrupt bit will change regardless of condition of interrupt
enable (I0) status. An interrupt in the GPI in slot 12 in the ACLink
will follow this bit change when interrupt enable (I0) is unmasked.
Interrupt Cause
00 = Reserved
01 = Sense Cycle Complete, sense info available.
10 = Change in GPIO input status
11 = Sense Cycle Complete and Change in GPIO input status.
These bits will reflect the general cause of the first interrupt event
generated. It should be read after interrupt status has been
confirmed as interrupting. The information should be used to scan
possible interrupting events in proper pages.
Sense Cycle
0 = Sense Cycle not in Progress
1 = Sense Cycle Start.
Writing a 1 to this bit causes a sense cycle start if supported. If
sense cycle is not supported this bit is read only.
Interrupt Enable
0 = Interrupt generation is masked.
1 = Interrupt generation is un-masked.
The driver should not un-mask the interrupt unless ensured by the
AC‘97 controller that no conflict is possible with modem slot 12 -
GPI functionality. Some AC’97 2.2 compliant controllers will not
likely support audio CODEC interrupt infrastructure. In either case,
Software should poll the interrupt status after initiating a sense
cycle and wait for Sense Cycle Max Delay to determine if an
interrupting event has occurred.
I1
PG3
D11
D3
I0
STAC9752A/9753A
Description
PG2
D10
D2
Reserved
PG1
D9
D1
PC AUDIO
PG0
V 1.5 1206
D8
D0