IDTSTAC9753AXNAED1X IDT, Integrated Device Technology Inc, IDTSTAC9753AXNAED1X Datasheet - Page 27

• Manufacturer Part Number: IDTSTAC9753AXNAED1X
• Description: IC CODEC AC'97 MIC/JACK 32-QFN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec '97r

Specifications of IDTSTAC9753AXNAED1X

• Resolution (bits): 20 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: Yes
• S/n Ratio, Adcs / Dacs (db) Typ: 85 / 92
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 32-QFN
• Single Supply Voltage (typ): 3.3/5V
• Single Supply Voltage (min): 3.135V
• Single Supply Voltage (max): 3.465/5.25V
• Package Type: VFQFPN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: STAC9753AXNAED1X

IDT™
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
STAC9752A/9753A
AC’97 2.3 CODECS WITH STEREO MICROPHONE & UNIVERSAL JACK
4.4.
4.3.1.
4.3.2.
4.3.3.
Clocking for Multiple CODEC Implementations
Primary CODEC Addressing
Primary AC‘97 CODECs respond to register read and write commands directed to CODEC ID 00
(see Section 4 for details of the Primary and Secondary CODEC addressing protocols). Primary
devices must be configurable (by hardwiring, strap pin(s), or other methods) as CODEC ID 00, and
reflect this in the two-bit CODEC ID field(s) of the Extended Audio and/or Extended Modem ID Reg-
ister(s).
The Primary CODEC may either drive the BIT_CLK signal or consume a signal provided by the Dig-
ital Controller or other clock generator.
Secondary CODEC Addressing
Secondary AC‘97 CODECs respond to register read and write commands directed to CODEC IDs
01, 10, or 11. Secondary devices must be configurable (via hardwiring, strap pin(s), or other meth-
ods) as CODEC IDs 01, 10, or 11 in the two-bit field(s) of the Extended Audio and/or Extended
Modem ID Register(s).
CODECs configured as Secondary must power up with the BIT_CLK pin configured as an input.
Using the provided BIT_CLK signal is necessary to ensure that everything on the AC-Link is syn-
chronous. BIT_CLK is the clock source (multiplied by 2 so that the internal rate is 24.576MHz).
CODEC ID Strapping
Audio CODECs in the 48-pin package use pins 45 and 46 (defined as ID0# and ID1#) as strapping
(i.e. configuration) pins to configure the CODEC ID. The ID0# and ID1# strapping bits adopt inverted
polarity and default to 00 = Primary (via a weak internal pullup) when left floating. This eliminates the
need for external resistors for CODECs configured as Primary, and maintains backward compatibil-
ity with existing layouts that treat pins 45 and 46 as “no connect” or a capacitor connected to ground.
Pulldowns are typically 0-10 K
To keep the system synchronous, all Primary and Secondary CODEC clocking must be derived from
the same clock source, so they are operating on the same time base. In addition, all AC-Link proto-
col timing must be based on the BIT_CLK signal, to ensure that everything on the AC-Link will be
synchronous.
CID1 (pin 46)
pulldown
pulldown
NC
NC
Table 3. Recommended CODEC ID strapping
and connected to Digital (not Analog) Ground.
27
CID0 (pin 45)
pulldown
pulldown
NC
NC
STAC9752A/9753A
Secondary ID 01
Secondary ID 10
Secondary ID 11
Configuration
Primary ID 00
PC AUDIO
V 1.5 1206