IDT92HDW74C15PRGXC1X IDT, Integrated Device Technology Inc, IDT92HDW74C15PRGXC1X Datasheet - Page 15

• Manufacturer Part Number: IDT92HDW74C15PRGXC1X
• Description: IC AUDIO CODEC HD 6CH 48-TQFP
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec, HDr

Specifications of IDT92HDW74C15PRGXC1X

• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 3
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 86 / 90
• Dynamic Range, Adcs / Dacs (db) Typ: 86 / 90
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 3.8 V ~ 4.2 V; 4.28 V ~ 4.73 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 92HDW74C15PRGXC1X

SIX CHANNEL HD AUDIO CODEC, PREMIUM WLP 3/4 COMPLIANT
D0-D3
D0
D1-D2
D3
D0-D3
D0-D3
AFG Power
92HDW74C1
SIX CHANNEL HD AUDIO CODEC, PREMIUM WLP 3/4 COMPLIANT
AFG Power
State
State
De-Asserted (High)
Asserted (Low)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
RESET#
Asserted (Low)
Note: Peak to peak jitter is currently limited to less than 4.5nS (half of the internal master clock cycle)
which does not meet the IEC-60958-3 0.05UI requirement at 192KHz.
The two SPDIF ouput converters can not be aligned in phase with the DACs. Even when attached to
the same stream, the two SPDIF output converters may be misaligned with respect to their frame
boundaries.
SPDIF Outputs on pins 48 and 40 are outlined in tables below. Pin 47 behavior table resides in the
EAPD section
RESET#
Enabled
GPIO 3
Enable
Output Enable
Table 4. SPDIF OUT 0 (Pin 48) Behavior
Table 5. SPDIF OUT 1 (Pin 40) Behavior
-
Disabled
Disabled
Enabled
Enabled
Enabled
Enabled
-
-
Output
Enable
-
-
Converter Dig
15
Disabled
Enabled
Enabled
Enable
-
-
-
-
-
Dig Enable
Converter
-
-
Stream ID
Stream ID
1-15
0
-
-
-
-
-
-
-
-
92HDW74C1
Active - Pin drives SPDIF-format,
Hi-Z (internal pull-down enabled)
Hi-Z (internal pull-down enabled)
Hi-Z (internal pull-down enabled)
Hi-Z (internal pull-down enabled)
Hi-Z (internal pull-down enabled)
retained until the rising edge of
retained until the rising edge of
otherwise the previous state is
Active - Pin drives SPDIFOut0
otherwise the previous state is
configuration (internal pull-up
Active - Pin drives 0 (internal
Active - Pin drives 0 (internal
immediately after power on,
data (internal pull-down NA)
immediately after power on,
Active - Pin reflects GPIO7
but data is zeroes (internal
pull-down NA)
pull-down NA)
pull-down NA)
Pin Behavior
Pin Behavior
RESET#
RESET#
enabled)
PC AUDIO
V 1.0 03/08