IDT92HD71B7X5NLGXB3X8 IDT, Integrated Device Technology Inc, IDT92HD71B7X5NLGXB3X8 Datasheet - Page 18

• Manufacturer Part Number: IDT92HD71B7X5NLGXB3X8
• Description: IC AUDIO CODEC HD 4CH 48-VFQFPN
• Manufacturer: IDT, Integrated Device Technology Inc
• Type: Audio Codec, HDr

Specifications of IDT92HD71B7X5NLGXB3X8

• Resolution (bits): 24 b
• Number Of Adcs / Dacs: 2 / 2
• Sigma Delta: No
• S/n Ratio, Adcs / Dacs (db) Typ: 86 / 90
• Dynamic Range, Adcs / Dacs (db) Typ: 86 / 90
• Voltage - Supply, Analog: 3.14 V ~ 3.47 V; 3.8 V ~ 4.2 V; 4.28 V ~ 4.73 V; 4.75 V ~ 5.25 V
• Voltage - Supply, Digital: 3.14 V ~ 3.47 V
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 48-VFQFN
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 92HD71B7X5NLGXB3X8

4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
D0-D3
0
92HD71B7
4-CHANNEL HD AUDIO CODEC OPTIMIZED FOR LOW POWER
Digital Mics
AFG Power
State
1.4.13. Digital Microphone Support
N/A
Data Sample
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
De-Asserted (High)
Asserted (Low)
The digital microphone interface permits connection of a digital microphone(s) to the CODEC via the
DMIC0, DMIC1, and DMIC_CLK 3-pin interface. The DMIC0 and DMIC1 signals are inputs that carry
individual channels of digital Mic data to the ADC. In the event that a single microphone is used, the
data is ported to both ADC channels.
The DMIC_CLK output is controllable from 4.704Mhz, 3.528Mhz, 2.352Mhz, 1.176Mhz and is syn-
chronous to the 24Mhz internal clock. The default frequency is 2.352Mhz.
92HD71B7 supports the following digital microphone configurations:
RESET#
N/A
ADC Conn.
Table 8. Valid Digital Mic Configurations
GPIO Enable
Disabled
Disabled
Disabled
Enabled
No Digital Microphones
-
Table 7. EAPD Behavior
Output Enable
18
Disabled
Disabled
Enabled
-
-
EAPD Power
D2-D3
D0-D1
State
-
-
-
Notes
92HD71B7
output (internal pull-down enabled)
Active - Pin drives the value of the
Hi-Z (internal pull-down enabled)
Hi-Z (internal pull-down enabled)
Active - Pin Drives SPDIFOut0/1
retained until the rising edge of
otherwise the previous state is
configuration (internal pull-up
EAPD bit (internal pull-down
immediately after power on,
Active - Pin reflects GPIO0
Pin Behavior
RESET#
enabled)
enabled)
PC AUDIO
V 1.0, 01/08