STLC5048TR STMicroelectronics, STLC5048TR Datasheet
STLC5048TR
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STLC5048TR Summary of contents
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Fully programmable four-channel codec and filter Features ■ Fully programmable monolithic 4-channel codec/filter ■ Single +3.3 V supply ■ A/m law programmable ■ Linear coding (16 bits) option ■ PCM highway format automatically detected: 1.536 or 1.544 MHz, 2.048, 4.096, ...
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Contents Contents 1 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STLC5048 5.11 Configuration register (CONF 5.12 ...
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Contents 8 Command description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STLC5048 List of tables Table 1. Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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List of tables Table 49. Transmit time slot ch #2 (DXTS2) bits . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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STLC5048 List of figures Figure 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...
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Block diagram 1 Block diagram Figure 1. Block diagram VFRO0 VFX10 VFRO1 VFX11 VFRO2 VFX12 VFRO3 VFX13 8/64 VCC VEE VDD VSS SUB ANALOG FRONT END DIGITAL PROCESSOR D/A CH0 16 GR0 A/D PLL CH0 BLOCK A/U LAW GX0 DECODER ...
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STLC5048 2 Absolute maximum ratings and operating conditions Table 1. Absolute maximum ratings Symbol Digital input pin voltage IN VAin Analog input pin voltage (V T Storage ...
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Pin assignments and descriptions 3 Pin assignments and descriptions Figure 2. Pin assignments (top view) Table 4. I/O definitions 10/ N.C. 2 N.C. 3 INT ...
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STLC5048 Table 5. Pin descriptions No. Name Type Analog pins 33 VFRO0 AO 39 VFRO1 AO 42 VFRO2 AO 48 VFRO3 AO 35 VFXI0 AI 38 VFXI1 AI 43 VFXI2 AI 46 VFXI3 AI 40 CAP 34 ITH AO 47 ...
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Pin assignments and descriptions Table 5. Pin descriptions (continued) No. Name Type 13 MCLK DI 12 TSXA ODO 11 DXA DTO 10 DRA DI 24 IO5 DIO 62 IO6 DIO 61 IO7 DIO 60 IO8 DIO 59 IO9 DIO 58 ...
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STLC5048 Table 5. Pin descriptions (continued) No. Name Type CCLK INT ODO 17 TSXB ODO 15 DXB DTO 16 DRB DI Not connected 2, 18, 63, 1 N.C. ...
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Functional description 4 Functional description The STLC5048 is a fully programmable device with embedded ROM and RAM. The ROM is used to contain the default state coefficients for the programmable filters, while the RAM is used to load the desired ...
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STLC5048 4.3 Ringing state This state can be used during the ringing phase in order to transmit a low frequency ringing signal (25-50 Hz). In order to obtain a 1 Vrms ringing signal at VFRO output a digital signal DR ...
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Functional description VFXI input must be AC coupled to the signal; the voltage swing allowed is 1.4 Vpp when the preamplifier gain is set and 0.93 Vpp when the gain is 3.52 dB; higher levels must be ...
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STLC5048 VFRO output, referred to AGND must be AC coupled to the load, referred to VSS, to prevent a DC current flow. In order to get the best noise performances it is recommended to keep GRX value as close as ...
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Functional description Table 6. Instruction byte structure First byte (address or command ID R R/W=0: Write operation R/W=1: Read operation I6..I0: Instruction identifier: it can be a register address or a command identifier. The number ...
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STLC5048 period specified by means of T_OUT command, an internal time out rejects the instruction. The time-out time is verified between two consecutive MCU interface access (between the falling edge of the CS and the following rising edge). This feature ...
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Functional description 4.11 SLIC control interface The device provides 12 I/O pins and 4 CS signals. The interface can work in dynamic or static mode. This can be selected by means of STA bit of the CONF register: ● Dynamic ...
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STLC5048 Table 7. Register addresses (continued) Addr 08h 09h 0Ah 0Bh 10h 11h 12h 13h 14h 20h 21h 23h 25h 26h 27h 2Ah 2Bh 2Ch 2Dh 2Eh 50h 51h 52h 53h 54h 55h 56h 57h 58h 59h 5Ah 5Bh 5Ch ...
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Functional description Table 7. Register addresses (continued) Addr 60h 61h 70h 71h 22/64 Name TONEG Tone generation reg. COEFST Coefficient state reg. SWRID Software rev. ID code HWRID Silicon revision ID code STLC5048 Description ...
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STLC5048 5 Register description 5.1 I/O direction register (DIR) Addr=00h; reset value=00h Addr=01h; reset value=X0h Table 8. I/O direction register (DIR) bits BIt7 Bit6 R Table 9. I/O direction register (DIR) bits BIt7 Bit6 R/W 0 ...
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Register description Table 12. Static I/O data register channel #0 (DATA0) bits BIt7 Bit6 R Table 13. Static I/O data register channel #0 (DATA0) bits Bit7 Bit6 R/W 0 DS11..0 are transferred to the corresponding I/O ...
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STLC5048 CIO0..3=0 The CS0.. static input, DATA is written in DATA2 register bits 0..3. CIO0..3=1 The CS0.. static output, DATA is taken from DATA2 register bits 0..3. 5.4 I/O data register channel #2 (DATA2) Addr=06h; reset ...
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Register description Table 21. Dynamic I/O data register channel #3 (data3) bits Bit7 Bit6 R/W 0 When CS3 is active D311..0 are transferred to the corresponding I/O pins configured as outputs (see DIR register). For the I/O pins configured as ...
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STLC5048 TA7..0 and TB7..0, contents of PCHKA and PCHKB registers, define the minimum duration of input A and B to generate interrupt; spurious transitions shorter than the programmed value are ignored. The time width can be calculated according to the ...
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Register description 5.8 Interrupt mask register for I/O port (DMASK) Addr=11h; reset value=FFh Addr=12h; reset value=XFh Table 26. Interrupt mask register for I/O port (DMASK) bits Bit7 Bit6 R Table 27. Interrupt mask register for I/O ...
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STLC5048 For static I/O configuration, MCn bits are the interrupt mask bits related to CSn that are configured as I/O lines. ● MC0=1: The corresponding I/O cannot generate interrupt independently of DMASK setting. ● MC0=0: The corresponding I/O can generate ...
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Register description 5.11 Configuration register (CONF) Addr=20h; reset value=BFh Table 30. Configuration register (CONF) bits BIt7 Bit6 R/W 0 RES LIN ● RES=0: Normal operation ● RES=1: Device reset: I/0n and Csn are all inputs H.I. (equivalent to ...
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STLC5048 5.13 Synchronous check register (SYNCK) Addr=23h; reset value=E4h Read-only Table 32. Synchronous check register (SYNCK) bits Bit7 Bit6 This register contains a fixed code (E4h) that can be read to check the synchronization of the ...
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Register description The checksum value is calculated every time the CKSTART instruction is performed and the result is available after a proper delay (max 400 μs). This register contains the checksum value calculated on the contents of the following coefficient ...
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STLC5048 Overall transmit gain depends on combination of TXG and GTXn registers. 5.18 Receive amplifier gain register (RXG) Addr=2Ch; reset value=00h Table 38. Receive amplifier gain register (RXG) bits Bit7 Bit6 R ● Rn =0,Rn =0: ...
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Register description 5.20 SLIC off-hook threshold register (ITH) Addr=2Eh; reset value=00h Table 40. SLIC off-hook threshold register (ITH) bits Bit7 Bit6 R ● D3.. Programmed value ● D3.. Programmed value ...
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STLC5048 Table 43. PCM command register (PCMCOM) TPB and TPA bit combinations TPB ● RPAB = 0: Port A enabled (DRA input selected) ● RPAB = 1: Port B enabled (DRB input selected) ● ...
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Register description 5.23 Transmit time slot ch #0 (DXTS0) Addr=52h; reset value=00h Table 45. Transmit time slot ch #0 (DXTS0) bits Bit7 Bit6 R/W 1 EN0 T06 ● EN0=0: Selected transmit time slot on DX output is in H.I. ● ...
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STLC5048 Table 48. Transmit time slot ch #1 (DXTS1) time slots in linear mode 5.25 Transmit time slot ch #2 (DXTS2) Addr=54h; reset value=00h Table 49. Transmit time slot ch #2 (DXTS2) bits Bit7 Bit6 R/W 1 ...
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Register description If linear mode is selected (LIN=1 of CONF register) the 16 bits will be carried out as follows: the 8 most significant bits in the programmed time slot, the 8 least significant bits in the following time slot. ...
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STLC5048 5.28 Receive time slot ch #1 (DRTS1) Addr=57h; reset value=00h Table 55. Receive time slot ch #1 (DRTS1) bits Bit7 Bit6 R/W 1 EN1 R16 ● EN1=0: Disable reception of selected time slot. ● EN1=1: Selected receive time slot ...
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Register description 5.30 Receive time slot ch #3 (DRTS3) Addr=59h; reset value=00h Table 59. Receive time slot ch #3 (DRTS3) bits Bit7 Bit6 R/W 1 EN3 R36 ● EN3=0: Disable reception of selected time slot. ● EN3=1: Selected receive time ...
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STLC5048 5.32 PCMR data register (PCMRD) Addr=5Ch; reset value=00h Addr=5Dh; reset value=00h Read-only Table 63. PCMR data register (PCMRD) bits Bit7 Bit6 Table 64. PCMR data register (PCMRD) bits Bit7 Bit6 1 1 D15 D14 This ...
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Register description 5.34 Tone generation register (TONEG) Addr=60h; reset value=00h Table 66. Tone generation register (TONEG) bits Bit7 Bit6 R ● Tn =0,Tn =0: No tone is generated ● Tn =1,Tn ...
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STLC5048 5.37 Hardware revision ID code (HWRID) Addr=71h; Read-only. Table 69. Hardware revision ID code (HWRID) bits Bit7 Bit6 This register contains the silicon revision code identifier. Bit5 Bit4 Bit3 ...
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Single byte instruction 6 Single byte instruction Table 70. Single byte instruction Name REACOM CKSTART 6.1 Realignment command (REACOM) This single instruction is used to realign the MCU interface in case of out of synchronization. This instruction must be executed ...
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STLC5048 7 Command list Table 73. Command list Name BLKEN KDF AFECFF T_OUT GRX GTX RFC XFC BFC ZFC (*) For these two commands, the bit set in the COMEN register are not considered. Description Block enable KD filter AFE ...
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Command description 8 Command description Each command is transferred on every channel that has the proper bit in the COMEN register set to 1. 8.1 Block enable command (BLKEN) Reset value=00h The command is used to enable/disable the B, Z, ...
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STLC5048 8.3 AFE coefficient (AFE_CFF) Reset value = AA00h Table 76. AFE coefficient (AFE_CFF) bits Bit7 Bit6 R/W 0 KA31 KA30 KAn0, KAn1 = KA coefficient for Ch #n According to the value of each couple of bits, the KA ...
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Command description 8.5 Receive gain (GRX) Table 78. Receive gain (GRX) bits Bit7 Bit6 R/W 1 ● 00h: Stop any received signal to reach the VFRO0 analog output. In order to open the impedance synthesis feedback it’s necessary to mute ...
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STLC5048 8.8 X filter coefficient (XFC) The register is used to set the 17 coefficients (each of 16 bits) of the X filter of the channel #n. Table 81. X filter coefficient (XFC) bits Bit7 Bit6 R/W 1 8.9 B ...
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Electrical characteristics 9 Electrical characteristics Typical value are for 25°C and nominal supply voltage. Minimum and maximum values are guaranteed over the temperature 0-70°C range by production testing and supply voltage range shown in the operating ranges. Performances over -40 ...
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STLC5048 Table 84. Electrical characteristics (continued) Symbol Parameter Hold time MCLK low to Thbf FSX/R high or low Setup time FSX/R high to Tsfb MCLK low Delay time, MCLK high to Tdmd data valid Delay time from MCLK(8) low Tdmz ...
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Electrical characteristics Table 84. Electrical characteristics (continued) Symbol Parameter Delay time CCLK9 tddz high to CO high impedance SLIC control interface timing (dynamic configuration; see Tcs Chip select repetition rate tcsw Chip select pulse width tdcsl Data out ...
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STLC5048 Table 84. Electrical characteristics (continued) Symbol Parameter Transmit noise psophometric NPT weighted @ 0 dBr, (2) Zadm=600 ohm (3) DAX Absolute delay Single frequency distortion DPXM (Mu Law 0 dBm0 sinewave @ 1004 Hz) Single frequency distortion (A DPXA ...
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Electrical characteristics Table 84. Electrical characteristics (continued) Symbol Parameter Receive noise C message NCR weighted (Mu Law) Receive noise psophometric NPR weighted (A Law) (2) DAR Absolute delay Single frequency distortion DPR1 (0dBm0 sinewave, 1004 Hz) GSPR Out of band ...
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STLC5048 Figure 6. PCM interface timing MCLK T HBF T SFB FSX T DMD DX T DMT TSX T SFB T HBF FSR DR Figure 7. Serial control port timing CCLK HCS SSC ...
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Electrical characteristics Figure 9. Group delay distortion mask 56/64 Delay (μs) 600 500 400 Rx direction 300 200 100 0 500 1000 1500 Delay (μs) 600 500 400 Tx direction 300 200 100 0 500 1000 1500 STLC5048 Rx D02TL523 ...
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STLC5048 10 Package mechanical data In order to meet environmental requirements, ST offers these devices in ECOPACK® packages. These packages have a lead-free second level interconnect. The category of second level interconnect is marked on the package and on the ...
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Absolute gains in kit with L3235N/STLC3080 Appendix A Absolute gains in kit with L3235N/STLC3080 Figure 11. STLC5048 in kit with STLC3080 AC application diagram STLC5048 DR GRX CANCELING DX GTX Figure 12. STLC5048 in kit with L3235N AC application diagram ...
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STLC5048 Considering the TX gain we can proceed as follows for the gain calculation: ● TXG = 0 dB ● (As reported in the absolute gain levels with 61 Vrms at VFXI and GX=0 dB, the ...
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STLC5048 application diagrams Appendix B STLC5048 application diagrams Figure 14. STLC5048 plus L3235N/L324 kit application diagram 60/64 STLC5048 ...
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STLC5048 Figure 15. STLC5048 plus STLC3080 application diagram STLC5048 application diagrams 61/64 ...
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Power sequences Appendix C Power sequences C.1 Power-up sequence The DSP after an HW (M1= reset (CONF[7]= power-on reset (POR) has to perform the INIT program least one channel must be set ...
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... STLC5048 Ordering information Table 85. Order codes Order codes E-STLC5048 E- STLC5048TR 1. ECOPACK® (see Revision history Table 86. Document revision history Date 15-Jan-2003 02-Apr-2005 28-Nov-2007 (1) TQFP64 TQFP64 in Tape & Reel 10: Package mechanical data ) Revision 7 First issue on www.st.com. Changed figures 13 and 14: – Figure 13 added a resistance 6.8 MΩ between pin VFXI0- ...
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