STLC5048TR STMicroelectronics, STLC5048TR Datasheet - Page 26

IC CODEC/FILTER PROGR 4CH 64TQFP

STLC5048TR

Manufacturer Part Number
STLC5048TR
Description
IC CODEC/FILTER PROGR 4CH 64TQFP
Manufacturer
STMicroelectronics
Type
PCM Codec/Filterr
Datasheets

Specifications of STLC5048TR

Data Interface
PCM Audio Interface
Resolution (bits)
16 b
Number Of Adcs / Dacs
4 / 4
Sigma Delta
Yes
Voltage - Supply, Analog
3.3 V ~ 5 V
Voltage - Supply, Digital
3.3 V ~ 5 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

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Price
Part Number:
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Manufacturer:
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Manufacturer:
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0
Register description
5.6
26/64
Table 21.
When CS3 is active D311..0 are transferred to the corresponding I/O pins configured as
outputs (see DIR register). For the I/O pins configured as inputs the corresponding D311..0
will be written by the values applied to those pins while CS3 is low.
If bit4 of CONF register (STA) = 1
Static I/O mode:
Persistency check register (PCHK-A/B)
Addr=0Ah; reset value=00h
Addr=0Bh; reset value=00h
Two input signal per channel, labelled A and B, are submitted to persistency check.
In dynamic mode (STA=0), A and B inputs of the four channels are sampled on the
multiplexed lines IO0 (pin 13) and IO1 (pin 14).
In static mode (STA=1) persistency check is performed on four pairs of lines, assigned to
each channel according to the table:
Table 22.
Table 23.
Table 24.
R/W
R/W
R/W
Bit7
Bit7
Bit7
TB7
TA7
D3
D3
change of status is detected.
3..0
3..0
=1: The corresponding CSn cannot generate interrupt.
=0: The corresponding I/O (programmed as input) can generate interrupt if a
CHAN #
Dynamic I/O data register channel #3 (data3) bits
A and B inputs of persistency check register in static mode
Persistency check register (PCHK-A/B) bits
Persistency check register (PCHK-A/B) bits
0
1
2
3
Bit6
Bit6
Bit6
TB6
TA6
0
0
0
Bit5
Bit5
Bit5
TB5
TA5
0
0
0
Bit4
Bit4
Bit4
TB4
TA4
0
0
0
IO
IO
IO
IO
10
Input A
0
4
6
(pin 19)
(pin 17)
(pin 48)
(pin 44)
D3
Bit3
Bit3
Bit3
TB3
TA3
1
1
1
11
D3
Bit2
Bit2
Bit2
TB2
TA2
0
0
0
10
IO
IO
IO
IO
Bit1
Bit1
Bit1
D3
TA1
TB1
11
Input B
1
5
7
0
1
1
(pin 14)
(pin 18)
(pin 47)
(pin 43)
9
STLC5048
Bit0
Bit0
Bit0
TB0
D3
TA0
1
0
1
8

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