ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 126

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

ENC424J600/624J600
Copy operations are performed starting with the first
byte or word at the source address and incrementing
forward. It is legal to use the DMA to move a block of
data backwards in memory, even if the source and
destination memory ranges overlap. For example, if a
65-byte packet of data was located starting at memory
address 0001h, and the application wished to move the
whole packet to address 0000h, it may simply program
EDMAST to 0001h and EDMADST to 0000h. The
non-overlapping byte at address 00041h will remain
unchanged. Similarly, it is also legal to move a block of
data from an even aligned address to an immediately
prior odd aligned address. For example, moving from
0002h to 0001h will work correctly with the final
non-overlapping byte again remaining unchanged.
Since copy operations start at the beginning of the
source address range and increment forward (as
opposed to starting at the end of the source range and
incrementing backwards), it is not possible to move
blocks of data forward towards a higher memory
address if the source and destination address ranges
overlap. To perform this operation, the application must
copy the source data to a non-overlapping temporary
buffer location and then copy it from the temporary
buffer to the final destination.
14.2
The DMA module can compute an IP checksum value
over a given range of bytes. Checksums can be calcu-
lated over a specific range of memory, or simultaneously
as a copy operation progresses. Remember to verify
that the values of ERXST, EUDAND and EUDAST (if
applicable) are selecting the desired buffer wrapping
configuration before starting any checksum operation.
The checksum calculation logic treats the source data
as a series of 16-bit big-endian integers. If the source
data has an odd number of bytes, a padding byte of 00h
will be added for the calculation. (This byte is not
copied to the destination if the checksum is part of a
copy operation.) The calculated checksum is the 16-bit
one’s complement of the one’s complement sum of all
16-bit integers in the series. For example, if the bytes
included in the checksum were {89h, ABh, CDh}, the
checksum would begin by calculating 89ABh + CD00h.
A carry would occur and the result would be 56ACh.
That value would be complemented to yield a
checksum of A953h.
To calculate a checksum without copying data:
1.
2.
3.
4.
5.
DS39935C-page 124
Verify that DMAST (ECON1<5>) is clear,
indicating that the module is Idle.
Clear DMACPY (ECON1<4>) to prevent a copy
operation.
Clear DMANOCS (ECON1<2>) to select a
checksum calculation.
Clear DMACSSD (ECON1<3>) to use the
default seed of 0000h. See the paragraph below
to seed a checksum with another value.
Set EDMAST to point to the source address.
Checksum Calculations
6.
7.
8.
9.
To calculate a checksum while copying data:
1.
2.
3.
4.
5.
6.
7.
8.
9.
10. Read the computed checksum from EDMACS.
The checksum can be seeded with a previous value if
required. Seeding may be useful when attempting to
compute a checksum over non-contiguous blocks of
data. To seed the checksum, set DMACSSD
(ECON1<3>) before initiating the operation. The
checksum calculation is seeded with the one’s
complement of the value contained in EDMACS prior to
the start of the DMA operation.
14.3
The DMA controller can operate at any time, without
any regard to other modules in the device. Several
factors affect its speed of operation, including:
• Ethernet transmit and receive utilization,
• SPI or PSP read or write operations to the SRAM
• Operating mode (copy versus checksum only)
• Even-to-odd or odd-to-even source and
Neglecting the time it takes software to program the
DMA control SFRs, under typical unloaded conditions,
the DMA will have a Checksum Only mode throughput
of 100 Mbytes/second. Copy mode (with or without
checksum) will achieve a typical throughput of
50 Mbytes/second when the source and destination
addresses share the same alignment. Differing source
and destination alignment would slow the process to
33.3 Mbytes/second.
Worst case conditions can cut the DMA throughput by
no more than half of the typical values.
especially at 100 Mbps
destination addresses (Copy mode)
Set EDMALEN to indicate the length of the input
data.
Set DMAST to initiate the operation.
Wait for the hardware to clear DMAST to indicate
completion. If the DMA interrupt is enabled, it will
be triggered when DMAST is cleared.
Read the computed checksum from EDMACS.
Verify that DMAST is clear, indicating that the
module is Idle.
Set DMACPY to select a copy operation.
Clear DMANOCS to select a checksum
calculation.
Clear DMACSSD to use the default seed of
0000h. See the paragraph below to seed a
checksum with another value.
Set EDMAST to point to the source address.
Set EDMADST to point to the destination
address.
Set EDMALEN to indicate the number of bytes
to copy.
Set DMAST to initiate the operation.
Wait for the hardware to clear DMAST to indicate
completion. If the DMA interrupt is enabled, it will
be triggered when DMAST is cleared.
DMA Performance
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