ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 79

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

REGISTER 8-1:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15
bit 14
bit 13
bit 12
bit 11-8
bit 7
bit 6
Note 1:
AUTOFC
ETHEN
R/W-1
R/W-0
Reset value on POR events only. All other Resets leave these bits unchanged.
ETHEN: Ethernet Enable bit
1 = Device is enabled (normal operation)
0 = Device is disabled (reduced power)
STRCH: LED Stretching Enable bit
1 = Stretch transmit, receive and collision events on LEDA and LEDB to 50 ms
0 = LEDA and LEDB outputs show real-time status without stretching
TXMAC: Automatically Transmit MAC Address Enable bit
1 = MAADR1-MAADR6 registers are automatically inserted into the source address field of all
0 = No automatic source address insertion
SHA1MD5: SHA-1/MD5 Hash Control bit
1 = Hashing engine computes a SHA-1 hash
0 = Hashing engine computes an MD5 hash
COCON<3:0>: CLKOUT Frequency Control bits
1111 = 50 kHz nominal ((4 * F
1110 = 100 kHz nominal ((4 * F
1101 = No output (DC sinking to V
1100 = 3.125 MHz nominal ((4 * F
1011 = 4.000 MHz nominal ((4 * F
1010 = 5.000 MHz nominal ((4 * F
1001 = 6.250 MHz nominal ((4 * F
1000 = 8.000 MHz nominal ((4 * F
0111 = 8.333 MHz nominal ((4 * F
0110 = 10.00 MHz nominal ((4 * F
0101 = 12.50 MHz nominal ((4 * F
0100 = 16.67 MHz nominal ((4 * F
0011 = 20.00 MHz nominal ((4 * F
0010 = 25.00 MHz nominal ((4 * F
0001 = 33.33 MHz nominal ((4 * F
0000 = No output (DC sinking to V
AUTOFC: Automatic Flow Control Enable bit
1 = Automatic flow control is enabled
0 = Automatic flow control is disabled
TXRST: Transmit Logic Reset bit
1 = Transmit logic is held in Reset. TXRTS (ECON1<1>) is automatically cleared by hardware when
0 = Transmit logic is not in Reset (normal operation)
STRCH
TXRST
R/W-1
R/W-0
transmitted packets
this bit is set.
ECON2: ETHERNET CONTROL REGISTER 2
W = Writable bit
‘1’ = Bit is set
TXMAC
RXRST
R/W-0
R/W-0
OSC
SHA1MD5
ETHRST
OSC
R/W-0
R/W-0
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
OSC
)/2000)
SS
SS
)/1000)
)
)
)/32)
)/25)
)/20)
)/16)
)/12.5); duty cycle is not 50%
)/12)
)/10)
)/8)
)/6)
)/5)
)/4)
)/3)
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
MODLEN1
COCON3
ENC424J600/624J600
R/W-1
R/W-0
(1)
(1)
MODLEN0
COCON2
R/W-0
R/W-0
(1)
x = Bit is unknown
AESLEN1
COCON1
R/W-1
R/W-0
(1)
DS39935C-page 77
AESLEN0
COCON0
R/W-1
R/W-0
(1)
bit 8
bit 0