ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 38

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

setting up a circular FIFO within the general purpose
purpose or receive buffer cases. This is because the
ENC424J600/624J600
3.5.5.2
As with the general purpose pointers, operations with
ERXDATA
ERXWRPT Pointer to automatically increment by one
byte address. However, if the end of the receive buffer
area (5FFFh) is reached, the pointer will increment to
the start of the receive FIFO buffer area instead, as
defined by ERXST (Figure 3-7).
The receive wrapping rules for the ERXDATA interface
are identical to the buffer wrapping rules used by the
receive hardware. Therefore, this register interface is
ideally suited to reading packet data from the receive
buffer. The host controller can set the ERXRDPT value
at the start of a packet in the receive buffer and sequen-
tially read out the entire packet contents without having
to write to the ERXRDPT Read Pointer again.
EQUATION 3-2:
3.5.5.3
The user-defined buffer area is primarily useful for
area for use by TCP/IP stacks or other applications. The
wrap-around behavior of the user-defined buffer area is
somewhat more complicated than with the general
user-definable boundaries set by EUDAST and
EUDAND take priority over normal wrapping behavior.
Like other pointers, EUDAST and EUDAND are fully
user-configurable from the host microcontroller. Unlike
ERXST, which must not be modified while the receive
hardware is enabled, EUDAST and EUDAND can be
modified at any time.
EQUATION 3-3:
DS39935C-page 36
if ERXRDPT/ERXWRPT = 5FFFh, then
else
if EUDARDPT/EUDAWRPT = EUDAND, then
else if EUDARDPT/EUDAWRPT = 5FFFh, then
else
ERXRDPT/ERXWRPT = ERXST
ERXRDPT/ERXWRPT = ERXRDPT/ERXWRPT + 1
EUDARDPT/EUDAWRPT = EUDAST
EUDARDPT/EUDAWRPT = 0000h
EUDARDPT/EUDAWRPT = EUDARDPT/EUDAWRPT + 1
normally
Circular Wrapping with ERXDATA
Circular Wrapping with EUDADATA
POINTER INCREMENT LOGIC FOR ERXRDPT AND ERXWRPT
POINTER INCREMENT LOGIC FOR EUDARDPT AND EUDAWRPT
cause
the
ERXRDPT
or
FIGURE 3-7:
As in the previous instances, operations with
EUDADATA normally cause the EUDARDPT or
EUDAWRPT Pointer to automatically increment by one
byte address. If the value in EUDAND is reached, the
pointer will increment to the address specified by
EUDAST instead. However, if the end of memory
(5FFFh) is reached, and EUDAND is located at some
other address, the pointer will increment to the begin-
ning of memory (0000h). If EUDAND is set to 5FFFh,
the pointer address increments to the value of
EUDAST, instead of 0000h.
The increment behavior logic is explained in
Equation 3-3.
Circular RX FIFO
General Purpose
Unimplemented
CIRCULAR BUFFER
WRAPPING USING THE
ERXDATA WINDOW
 2010 Microchip Technology Inc.
Buffer
Buffer
0000h
ERXST – 1
ERXST
5FFFh