ENC424J600-I/ML Microchip Technology, ENC424J600-I/ML Datasheet - Page 31

• Manufacturer Part Number: ENC424J600-I/ML
• Description: IC ETHERNET CTRLR W/SPI 44-QFN
• Manufacturer: Microchip Technology

Specifications of ENC424J600-I/ML

• Package / Case: 44-QFN
• Controller Type: Ethernet Controller
• Interface: SPI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 96mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Input Voltage Range (max): 5.5 V
• Maximum Operating Temperature: + 85 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3 V to 3.6 V
• Supply Current (max): 117 mA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• For Use With: AC164132 - BOARD DAUGHTER PICTAIL ETHERNET
• Lead Free Status / Rohs Status: Lead free / RoHS Compliant

3.3.3
The MAC can be configured to perform automatic
back-to-back read operations on a PHY register. This
can reduce the host controller complexity when
periodic status information updates are desired.
To perform the scan operation:
1.
2.
REGISTER 3-1:
 2010 Microchip Technology Inc.
bit 15
bit 7
Legend:
R = Readable bit
-n = Value at POR
bit 15-13
bit 12-8
bit 7-5
bit 4-0
Write the address of the PHY register to read
from into the MIREGADR register. Make sure to
also set reserved bit 8 of this register.
Set the MIISCAN (MICMD<1>) bit. The scan
operation begins and the BUSY (MISTAT<0>)
bit is automatically set by hardware. The first
read operation will complete after 25.6 s. Sub-
sequent reads will be done at the same interval
until the operation is cancelled. The NVALID
(MISTAT<2>) bit may be polled to determine
when the first read operation is complete.
U-0
U-0
—
—
SCANNING A PHY REGISTER
Unimplemented: Read as ‘0’
Reserved: Write as ‘00001’ (01h)
Unimplemented: Read as ‘0’
PHREG<4:0>: MII Management PHY Register Address Select bits
The address of the PHY register which MII Management read and write operations will apply to.
U-0
U-0
—
—
MIREGADR: MII MANAGEMENT ADDRESS REGISTER
W = Writable bit
‘1’ = Bit is set
U-0
U-0
—
—
PHREG4
R/W-0
R/W-0
r
U = Unimplemented bit, read as ‘0’
‘0’ = Bit is cleared
ENC424J600/624J600
PHREG3
R/W-0
R/W-0
After setting the MIISCAN bit, the MIRD register will
automatically be updated every 25.6 s. There is no
status information which can be used to determine
when the MIRD registers are updated. On the SPI or
8-bit PSP interfaces, the host controller can only read
one register location at a time. Therefore, it must not be
assumed that the values of MIRDL and MIRDH were
read from the PHY at exactly the same time.
When the MIISCAN operation is in progress, the host
controller must not attempt to write to MIWR or start an
MIIRD operation. The MIISCAN operation can be
cancelled by clearing the MIISCAN (MICMD<1>) bit
and then polling the BUSY (MISTAT<0>) bit. New
operations may be started after the BUSY bit is cleared.
r
PHREG2
R/W-0
R/W-0
r
x = Bit is unknown
PHREG1
R/W-0
R/W-0
r
DS39935C-page 29
PHREG0
R/W-1
R/W-0
r
bit 8
bit 0