TDA8007BHL/C3,118 NXP Semiconductors, TDA8007BHL/C3,118 Datasheet
TDA8007BHL/C3,118
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935272525118
TDA8007BHLBE-T
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TDA8007BHL/C3,118 Summary of contents
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TDA8007BHL Multiprotocol IC card interface Rev. 8 — 11 January 2011 1. General description The TDA8007BHL is a cost-effective card interface for dual smart card readers. Controlled through a parallel bus, it meets all requirements of ISO 7816, GSM 11-11, ...
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... NXP Semiconductors – in Protocol 11.8 ETU – in Protocol 10.8 ETU Supports synchronous cards Current limitations in the event of short-circuit (pins I/O1, I/O2, VCC1, VCC2, RST1 and RST2) Special circuitry for killing spikes during power-on/power-off Supply supervisor for power-on/power-off reset Step-up converter (supply voltage from 2 V), doubler, tripler or follower ...
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... NXP Semiconductors Table 1. Quick reference data MHz; GND = XTAL Symbol Parameter V card supply output CC voltage I card supply output CC current sum of both card supply CC1 CC2 output currents SR slew rate on V (rise CC and fall) t deactivation cycle deact duration t activation cycle duration ...
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... NXP Semiconductors 6. Block diagram RSTOUT DELAY 22 nF INT ALE AD0 AD1 AD2 AD3 I/OAUX INTAUX Fig 1. Block diagram TDA8007BHL Product data sheet DDA 100 nF GND SAP SAM SUPPLY AND 48 SUPERVISOR ISO7816 42 UART TIME-OUT 31 COUNTER CLOCK 38 CIRCUIT 2 41 TDA8007B XTAL1 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors 7. Pinning information 7.1 Pinning Fig 2. 7.2 Pin description Table 3. Symbol RSTOUT I/OAUX I/O1 C81 PRES1 C41 CGND1 CLK1 V CC1 RST1 I/O2 TDA8007BHL Product data sheet 1 RSTOUT I/OAUX 2 I/O1 3 C81 4 5 PRES1 6 C41 CGND1 7 CLK1 CC1 10 RST1 11 I/O2 C82 12 Pin configuration ...
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... NXP Semiconductors Table 3. Symbol C82 PRES2 C42 CGND2 CLK2 V CC2 RST2 GND V UP SAP SBP V DDA SBM AGND SAM ALE INT INTAUX AD3 AD2 AD1 TDA8007BHL Product data sheet Pin description …continued Pin 28, 29, 30, 31, 32, 33, 34 All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors Table 3. Symbol AD0 XTAL2 XTAL1 DELAY 8. Functional description Remark: Throughout this document assumed that the reader is familiar with ISO7816 terminology. 8.1 Interface control The TDA8007BHL/C3 is sensitive to ESD in functional mode. This sensitivity is seen on pin ALE: an electrostatic discharge causes an edge on this pin and changes its mode of communication ...
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... NXP Semiconductors Fig 3. Fig 4. TDA8007BHL Product data sheet AD0 to AD3 WR RD Non-multiplexed bus configuration AD0 to AD3 Control with non-multiplex bus (read) All information provided in this document is subject to legal disclaimers. Rev. 8 — 11 January 2011 TDA8007BHL Multiprotocol IC card interface REC REGISTERS 001aam017 DATA OUT fce840 © ...
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... NXP Semiconductors Fig 5. Fig 6. 8.1.2 Multiplexed configuration The TDA8007BHL/C3 offers a multiplexed configuration in addition to a nun multiplexed configuration. The TDA8007BHL/C4 does not offer the multiplexed configuration. TDA8007BHL Product data sheet AD0 to AD3 Control with non-multiplex bus (Write with CS) AD0 to AD3 Control with non-multiplex bus (Write with EN) All information provided in this document is subject to legal disclaimers. Rev. 8 — ...
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... NXP Semiconductors If a microcontroller with a multiplexed address and data bus (such as 80C51) is used, then pins may be directly connected to port P0 to P7, see switching to the multiplexed bus configuration occurs only for TDA8007BHL/C3 rising edge is detected on signal ALE. In this event, pins AD0 to AD3 play no role and may be tied to VDD or ground. ...
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... NXP Semiconductors Cards 1, 2 and 3 have dedicated registers for setting the parameters of the ISO UART (see Figure Programmable Divider Register (PDR) Guard Time Register (GTR) UART Configuration register 1 (UCR1) UART Configuration Register 2 (UCR2) Clock Configuration Register (CCR) Cards 1 and 2 also have dedicated registers for controlling their power and clock configuration ...
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GENERAL CARD SELECT REGISTER HARD STATUS REGISTER CARD 1 PROGRAM DIVIDER REGISTER 1 GUARD TIME REGISTER 1 UART CONFIGURATION REGISTER 11 UART CONFIGURATION REGISTER 12 CLOCK CONFIGURATION REGISTER 1 POWER CONTROL REGISTER 1 Fig 9. Registers summary TIME-OUT REGISTER 1 ...
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... NXP Semiconductors 8.2.1 General registers 8.2.1.1 Card select register The Card Select Register (CSR) is used for selecting the card on which the UART will act, and also to reset the ISO UART. Table 4. 7 CS7 [1] Register value at reset: all significant bits are cleared after reset, except bits CS7 to CS4 which are set to their default value Table 5 ...
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... NXP Semiconductors Table 7. Bit When at least one of the bits PRTL2, PRTL1, PRL2, PRL1 or PTL is high, then INT is low. The bits having caused the interrupt are cleared when register HSR has been read-out. The same occurs with INTAUXL, if not disabled. In case of an emergency deactivation (by bits PRTL2, PRTL1, SUPL, PRL2, PRL1 or PTL), bit START (bit 0 in the PCR) is automatically reset by hardware ...
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... NXP Semiconductors Table 10. 7 TOL23 [1] Register value at reset: all bits are cleared after reset. 8.2.1.4 Time-out configuration register The Time-Out Configuration (TOC) register is used for setting different configurations of the time-out counter as given in Table 11; all other configurations are undefined. Table 11. 7 TOC7 [1] Register value at reset: all bits are cleared after reset ...
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... NXP Semiconductors Table 12. Register 75H 7CH 85H E5H F1H F5H The time-out counter is very useful for processing the clock counting during ATR, the Work Waiting Time (WWT) or the waiting times defined in protocol should be noted that the 200 and n ATR is done by hardware when the start session is set, specific hardware controls the functionality of BGT and protocols and a specific register is available for processing the extra guard time ...
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... NXP Semiconductors 8.2.2 ISO UART registers 8.2.2.1 UART Transmit Register (UTR) Table 13. 7 UT7 [1] Register value at reset: all bits are cleared after reset. When the microcontroller wants to transmit a character to the selected card, it writes the data in direct convention in the UART transmit register. The transmission: • ...
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... NXP Semiconductors 8.2.2.3 Mixed Status Register (MSR) The MSR relates the status of pin INTAUX, the cards presence contacts PRES1 and PRES2, the BGT counter, the FIFO empty indication and the transmit or receive ready indicator TBE/RBF. It also gives useful indications when switching the clock to or from 1 bits within register MSR act upon signal INT ...
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... NXP Semiconductors Table 16. Bit I/O bit RBF bit FE t SB(FE) INT RD CS bit CRED Fig 10. Minimum time between two read operations in register URR - non-multiplexed bus TDA8007BHL Product data sheet Description of MSR bits …continued Symbol Description PR1 card 1 present. Bit PR1 = 1 when card 1 is present. ...
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... NXP Semiconductors I/O bit TBE INT W(WR) bit CRED t WR(UTR) Fig 11. Minimum time between two write operations in register UTR - non-multiplexed bus W(RD) bit CRED T WR(TOC) Fig 12. Minimum time between two write operations in register TOC - non-multiplexed bus TDA8007BHL Product data sheet All information provided in this document is subject to legal disclaimers. ...
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... NXP Semiconductors I/O bit RBF bit FE t SB(FE) INT RD bit CRED Fig 13. Minimum time between two read operations in register URR - multiplexed mode TDA8007BHL/C3 I/O bit TBE INT WR t W(WR) bit CRED t WR(UTR) Fig 14. Minimum time between two write operations in register UTR - multiplexed mode TDA8007BHL/C3 ...
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... NXP Semiconductors 8.2.2.4 FIFO Control Registers (FSR) The FCR relates the parity error count and the FIFO length. Table 17. 7 FC7 [1] Register value at reset: all relevant bits are cleared after reset. Table 18. Bit 8.2.2.5 UART Status Register (USR) The USR is used by the microcontroller to monitor the activity of the ISO UART and that of the time-out counter ...
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... NXP Semiconductors If LCT mode is used for transmitting the last character, then bit TBE is not set at the end of the transmission. Table 19. 7 TO3 [1] Register value at reset: all relevant bits are cleared after reset. Table 20. Bit TDA8007BHL Product data sheet Register USR (address 0Eh; read only) ...
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... NXP Semiconductors 8.2.3 Card registers When cards are selected, the following registers may be used for programming some specific parameters. 8.2.3.1 Programmable Divider Register (PDR) The programmable divider registers PDR1, PDR2 and PDR3 are used for counting the cards clock cycles forming the ETU (see These are auto-reload 8-bit counters ...
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... NXP Semiconductors Table 23. Bit TDA8007BHL Product data sheet Description of UCR2 bits Symbol Description PDWN power-down mode. If bit PDWN is set by software, the crystal oscillator is stopped. This mode allows low power consumption in applications where this is required. During the Power-down mode not possible to select a card other than the one currently selected. ...
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... NXP Semiconductors Table 24. Baud rate selection using values F and D PSC = 31 3.58 MHz; PSC = 32: f CLK 31;12 31;12 31;18 9600 9600 6400 2 31;6 31;6 31;9 19200 19200 12800 3 31;3 31;3 38400 38400 31;1 31;1 115200 115200 9 [1] Example: 31;12 in the table means prescaler set to 31 and PDR set ...
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... NXP Semiconductors Table 27. Bit 8.2.3.5 Clock Configuration Registers (CCR) The clock configuration registers CCR1, CCR2 and CCR3 relate the clock signals: • For cards 1 and 2, register CCRx defines the clock for the selected card • For cards 1, 2 and 3, register CCRx defines the clock to the ISO UART. It should be ...
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... NXP Semiconductors Table 29. Bit Clock switching constraints: • the frequency delivered by the internal oscillator int • In case of f pin XTAL1 • When switching from (bits AC1 and AC0 must remain the same). When switching from clock stopped or vice verse, only bits CST and SHL must be changed • ...
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... NXP Semiconductors Table 31. Bit TDA8007BHL Product data sheet Description of PCRx bits Symbol Description PCR7 not used PCR6 not used C8 Contact 8 (C8). When writing to register PCR, pin C8 will output the value of bit C8. When reading from register PCR, bit C8 will store the value on pin C8 C4 Contact 4 (C4) ...
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Table 32. Addr Name R [2] 00 CSR R [2] 01 CCR R/W not used not used [2] 02 PDR R/W PD7 PD6 [2] 03 UCR R/W not used DISTBE/R BF [2] 05 ...
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... NXP Semiconductors 8.3 Supply CDELAY RSTOUT SUPL INT Fig 17. voltage supervisor The TDA8007BHL/C4 operates within a supply voltage range of 2 The supply pins are V Pins V DDA externally because of the large current spikes that the cards and the step-up converter can create. V Pins V DD that the contacts to the cards remain inactive during power-up and power-down ...
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... NXP Semiconductors 8.4 Step up converter Except for the V powered by V for the ISO contacts supply. When a card session is requested by the microcontroller, the sequencer first enables the step-up converter (a switched capacitors type) which is clocked by an internal oscillator at a frequency of approximately 2.5 MHz. ...
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... NXP Semiconductors 8.6 Activation sequence When the cards are inactive, pins V have a low impedance with respect to ground. The step-up converter is stopped. When everything is satisfactory (voltage supply, card present and no hardware problems), the system microcontroller may initiate an activation sequence of a present card. ...
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... NXP Semiconductors 8.7 Deactivation sequence When the session is completed, the microcontroller resets bit START at t then executes an automatic deactivation sequence (see 1. The card is reset by signal RST = low (t 2. Clock pulse CLK is stopped (t 3. Pins I/O, C4x and C8x fall Pin V 5. The step-up converter is stopped (t impedance to ground, if both cards are inactive ...
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... NXP Semiconductors 9. Limiting values Table 33. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage DD V analog supply voltage DDA V input voltage I P total power dissipation tot T storage temperature stg T junction temperature j V electrostatic discharge voltage ...
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... NXP Semiconductors Table 35. Characteristics …continued °C; unless otherwise specified. DD DDA amb Symbol Parameter I supply current in operating modem DD(oper) Voltage supervisor; see Figure 17 V threshold voltage on pin V th1 V hysteresis on V hys1 th1 Capacitor connection: pin DELAY V threshold voltage th2 V output voltage ...
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... NXP Semiconductors Table 35. Characteristics …continued °C; unless otherwise specified. DD DDA amb Symbol Parameter t rise time r t fall time f Clock output to the cards: pins CLK1 and CLK2 V output voltage in inactive mode o(inactive) I output current in inactive mode o(inactive) V low-level output voltage OL V high-level output voltage ...
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... NXP Semiconductors Table 35. Characteristics …continued °C; unless otherwise specified. DD DDA amb Symbol Parameter Configured as output V low-level output voltage OL V high-level output voltage output transition time (rise and fall o(r) o(f) time) Configured as input V low-level input voltage IL V high-level input voltage ...
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... NXP Semiconductors Table 35. Characteristics …continued °C; unless otherwise specified. DD DDA amb Symbol Parameter I shutdown current on pin RST RST(sd) I limitation current on pin RST RST(lim) T shutdown temperature sd Card presence inputs: pins PRES1 and PRES2 V low-level input voltage IL V high-level input voltage IH I low-level input leakage current ...
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... NXP Semiconductors Table 35. Characteristics …continued °C; unless otherwise specified. DD DDA amb Symbol Parameter input transition time (rise and fall time) C i(r) i(f) Configured as output V low-level output voltage OL V high-level output voltage output transition time (rise and fall o(r) o(f) time) ...
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... NXP Semiconductors Table 36. Timings 25°C; unless otherwise specified. DD DDA amb Symbol Parameter t WR low to bit CRED = 1 WR(TOC) Timing for multiplexed bus, only applicable for TDA8007BHL/C3 T XTAL1 cyle time CY(XTAL1) t ALE pulse width W(ALE) t address valid to ALE low AVLL t ALE low low ...
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V CARD CONNECTOR 1 C1 100 RSTOUT kΩ CGND1 100 nF CARD CONNECTOR 1 C3 100 ...
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100 C11 C51 RSTOUT C61 C21 C71 C31 I/OAUX C81 C41 PRES1 K1 K2 CARD_READ_LM01 CGND1 U1 CARD 1 Normally closed switch C2 100 ...
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... NXP Semiconductors 14. Package outline LQFP48: plastic low profile quad flat package; 48 leads; body 1 pin 1 index DIMENSIONS (mm are the original dimensions) A UNIT max. 0.20 1.45 1.6 mm 0.25 0.05 1.35 Note 1. Plastic or metal protrusions of 0.25 mm maximum per side are not included. OUTLINE VERSION ...
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... NXP Semiconductors 15. Handling information All input and output pins are protected against ElectroStatic Discharge (ESD) under normal handling. When handling Metal-Oxide Semiconductor (MOS) devices ensure that all normal precautions are taken as described in JESD625-A, IEC 61340-5 or equivalent standards. 16. Soldering of SMD packages This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “ ...
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... NXP Semiconductors 16.3 Wave soldering Key characteristics in wave soldering are: • Process issues, such as application of adhesive and flux, clinching of leads, board transport, the solder wave parameters, and the time during which components are exposed to the wave • Solder bath specifications, including temperature and impurities 16 ...
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... NXP Semiconductors Fig 23. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description”. TDA8007BHL Product data sheet maximum peak temperature = MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers ...
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... TDA8007B_7 20100512 • Modifications: The format of this data sheet has been redesigned to comply with the new identity guidelines of NXP Semiconductors. • Legal texts have been adapted to the new company name where appropriate. • Text changed to dedicate this data sheet to the C4 variant. ...
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... In no event shall NXP Semiconductors be liable for any indirect, incidental, punitive, special or consequential damages (including - without limitation - lost profits, lost savings, business interruption, costs related to the removal or ...
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... NXP Semiconductors’ specifications such use shall be solely at customer’s own risk, and (c) customer fully indemnifies NXP Semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive applications beyond NXP Semiconductors’ ...
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... NXP Semiconductors 20. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 Applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 Quick reference data . . . . . . . . . . . . . . . . . . . . . 2 5 Ordering information . . . . . . . . . . . . . . . . . . . . . 3 6 Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . 4 7 Pinning information . . . . . . . . . . . . . . . . . . . . . . 5 7.1 Pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 7.2 Pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 Functional description . . . . . . . . . . . . . . . . . . . 7 8.1 Interface control . . . . . . . . . . . . . . . . . . . . . . . . 7 8.1.1 Non-Multiplexed configuration . . . . . . . . . . . . . 7 8.1.2 Multiplexed configuration . . . . . . . . . . . . . . . . . 9 8 ...