LAN83C185-JT SMSC, LAN83C185-JT Datasheet - Page 23
![IC PHY 10/100 3.3V LP 64-TQFP](/photos/6/81/68190/lan83c185-jt_sml.jpg)
LAN83C185-JT
Manufacturer Part Number
LAN83C185-JT
Description
IC PHY 10/100 3.3V LP 64-TQFP
Manufacturer
SMSC
Datasheet
1.LAN83C185-JT.pdf
(60 pages)
Specifications of LAN83C185-JT
Controller Type
Ethernet Controller
Interface
MII
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
40mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
64-TQFP, 64-VQFP
Supply Voltage Range
2.97V To 3.63V
Digital Ic Case Style
TQFP
No. Of Pins
64
Operating Temperature Range
0°C To +70°C
Data Rate Max
100Mbps
Supply Voltage Max
3.6V
Rohs Compliant
Yes
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Other names
638-1009
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
LAN83C185-JT
Manufacturer:
Standard
Quantity:
2 077
Company:
Part Number:
LAN83C185-JT
Manufacturer:
ALTERA
Quantity:
513
Company:
Part Number:
LAN83C185-JT
Manufacturer:
Microchip Technology
Quantity:
10 000
High Performance Single Chip Low Power 10/100 Ethernet Physical Layer Transceiver (PHY)
Datasheet
SMSC LAN83C185
4.6.1
4.7
Auto-negotiation
MII
The MII includes 16 interface signals:
In MII mode, on the transmit path, the PHY drives the transmit clock, TX_CLK, to the controller. The
controller synchronizes the transmit data to the rising edge of TX_CLK. The controller drives TX_EN
high to indicate valid transmit data. The controller drives TX_ER high when a transmit error is detected.
On the receive path, the PHY drives both the receive data, RXD[3:0], and the RX_CLK signal. The
controller clocks in the receive data on the rising edge of RX_CLK when the PHY drives RX_DV high.
The PHY drives RX_ER high when a receive error is detected.
The purpose of the Auto-negotiation function is to automatically configure the PHY to the optimum link
parameters based on the capabilities of its link partner. Auto-negotiation is a mechanism for
exchanging configuration information between two link-partners and automatically selecting the highest
performance mode of operation supported by both sides. Auto-negotiation is fully defined in clause 28
of the IEEE 802.3 specification.
Once auto-negotiation has completed, information about the resolved link can be passed back to the
controller via the Serial Management Interface (SMI). The results of the negotiation process are
reflected in the Speed Indication bits in register 31, as well as the Link Partner Ability Register
(Register 5).
The auto-negotiation protocol is a purely physical layer activity and proceeds independently of the MAC
controller.
The advertised capabilities of the PHY are stored in register 4 of the SMI registers. The default
advertised by the PHY is determined by user-defined on-chip signal options.
The following blocks are activated during an Auto-negotiation session:
When enabled, auto-negotiation is started by the occurrence of one of the following events:
transmit data - TXD[3:0]
transmit strobe - TX_EN
transmit clock - TX_CLK
transmit error - TX_ER/TXD4
receive data - RXD[3:0]
receive strobe - RX_DV
receive clock - RX_CLK
receive error - RX_ER/RXD4
collision indication - COL
carrier sense - CRS
Auto-negotiation (digital)
100M ADC (analog)
100M PLL (analog)
100M equalizer/BLW/clock recovery (DSP)
10M SQUELCH (analog)
10M PLL (analog)
10M Transmitter (analog)
Hardware reset
Software reset
DATASHEET
23
Revision 0.8 (06-12-08)