COM20022I3V-HT SMSC, COM20022I3V-HT Datasheet - Page 32

• Manufacturer Part Number: COM20022I3V-HT
• Description: IC CTRLR ARCNET 2KX8 RAM 48-TQFP
• Manufacturer: SMSC
• Series: ARCNETr

Specifications of COM20022I3V-HT

• Controller Type: ARCNET Controller
• Interface: Differential
• Voltage - Supply: 4.5 V ~ 5.5 V
• Current - Supply: 65mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 48-TQFP, 48-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1004

Note*:
*DATA REGISTER AT 16 BIT ACCESS
6.2
6.2.1
Revision 09-27-07
REGISTER
DATA
ADDR
07-0
07-1
07-2
07-3
07-4
07-5
07-6
00
01
02
03
04
05
06
This bit can be written and read.
Internal Registers
The COM20022I contains 16 internal registers. Table 6.1 and Table 6.2 illustrate the COM20022I register
map. All undefined bits are read as undefined and must be written as logic "0".
Interrupt Mask Register (IMR)
The COM20022I is capable of generating an interrupt signal when certain status bits become true. A write
to the IMR specifies which status bits will be enabled to generate an interrupt. The bit positions in the IMR
are in the same position as their corresponding status bits in the Status Register and Diagnostic Status
Register. A logic "1" in a particular position enables the corresponding interrupt. The Status bits capable of
generating an interrupt include the Receiver Inhibited bit, DMAEND bit (new to the COM20022I), New Next
RESET
RI/TR1
RBUS-
(R/W)*
MODE
DATA
CYC7
TIM7/
MSB
NID7
TMG
TID7
W16
TC7/
RD-
P1-
C7
A7
D7
0
BIT
15
15
D
BIT
CCHEN
14
14
D
AUTO-
FOUR
NAKS
CYC6
TIM6/
NID6
TID6
TC6/
INC
C6
A6
D6
0
0
0
0
0
BIT
13
13
D
BIT
12
12
CKUP1
ITCEN/
D
RTRG
TXEN
CYC5
TIM5/
NID5
TID5
TC5/
C5
A5
D5
0
0
0
0
0
Table 6.2 - Write Register Summary
BIT
11
11
D
DATASHEET
CKUP0
BIT
10
10
RSYN/
GTTM
D
TIM4/
CYC4
RCV-
DMA
TID4
NID4
TC8/
TC4/
END
ET1
ALL
C4
D4
A4
0
0
0
BIT
WRITE
D9
9
Page 32
EXCNAK
BIT
DMAEN
D8
8
(R/W)*
CYC3
CKP3
DMA-
TIM3/
NID3
TID3
TC3/
MD1
ET2
C3
D3
EF
A3
0
BIT
D7
7
10 Mbps ARCNET (ANSI 878.1) Controller with 2Kx8 On-Chip RAM
BIT
D6
6
RECON
PLANE
BACK-
SYNC
CYC2
CKP2
DMA-
TIM2/
SUB-
NID2
TID2
MD0
TC2/
AD2
A10
NO-
C2
A2
D2
0
BIT
D5
5
BIT
D4
NEXTID
4
CKP1
TIM1/
CYC1
RCN-
SUB-
SUB-
TID1
NID1
TC1/
AD1
AD1
TM1
POL
NEW
TC-
C1
D1
A9
A1
0
BIT
D3
3
SWAP
SLOW-
DRQ-
TIM0/
CYC0
RCN-
BIT
SUB-
SUB-
TID0
NID0
TC0/
D2
LSB
AD0
AD0
TM0
POL
TTA
ARB
2
TA/
A0/
C0
D0
A8
0
BIT
D1
1
DMA COUNT
SMSC COM20022I
REGISTER
INTERRUPT
COMMAND
CONTROL
ADDRESS
ADDRESS
PTR HIGH
PTR LOW
URATION
BIT
D0
SUBADR
CONFIG-
NODEID
SETUP1
SETUP2
0
TENTID
DATA*
MASK
TEST
BUS
Datasheet
ADDR
04