ENC28J60-I/SS Microchip Technology, ENC28J60-I/SS Datasheet - Page 45
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ENC28J60-I/SS
Manufacturer Part Number
ENC28J60-I/SS
Description
IC ETHERNET CTRLR W/SPI 28SSOP
Manufacturer
Microchip Technology
Datasheet
1.ENC28J60SS.pdf
(98 pages)
Specifications of ENC28J60-I/SS
Package / Case
28-SSOP
Controller Type
Ethernet Controller, MAC/10Base-T
Interface
SPI
Voltage - Supply
3.1 V ~ 3.6 V
Current - Supply
160mA
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Input Voltage Range (max)
2.25 V to 5.5 V
Maximum Operating Temperature
+ 85 C
Minimum Operating Temperature
- 40 C
Mounting Style
SMD/SMT
Operating Supply Voltage
3.3 V
Supply Current (max)
180 mA
Package
28SSOP
Standard Supported
IEEE 802.3
Communication Mode
Full Duplex|Half Duplex
Network Interface
MII|MIIM
Data Rate
10 Mbps
Host Interface
SPI
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Available stocks
Company
Part Number
Manufacturer
Quantity
Price
Company:
Part Number:
ENC28J60-I/SS
Manufacturer:
MURATA
Quantity:
30 000
7.2
7.2.1
Assuming that the receive buffer has been initialized,
the MAC has been properly configured and the receive
filters have been configured to receive Ethernet
packets, the host controller should:
1.
2.
3.
After setting RXEN, the Duplex mode and the Receive
Buffer Start and End Pointers should not be modified.
Additionally, to prevent unexpected packets from arriv-
ing, it is recommended that RXEN be cleared before
altering the receive filter configuration (ERXFCON) and
MAC address.
FIGURE 7-3:
© 2008 Microchip Technology Inc.
If an interrupt is desired whenever a packet is
received, set EIE.PKTIE and EIE.INTIE.
If an interrupt is desired whenever a packet is
dropped due to insufficient buffer space, clear
EIR.RXERIF and set both EIE.RXERIE and
EIE.INTIE
Enable reception by setting ECON1.RXEN.
Receiving Packets
Packet N – 1
Packet N + 1
ENABLING RECEPTION
Packet N
SAMPLE RECEIVE PACKET LAYOUT
Address
106Ah
106Bh
106Ch
106Dh
106Eh
101Fh
1020h
1021h
1022h
1023h
1024h
1025h
1026h
1027h
1059h
rsv[23:16]
rsv[30:24]
data[m-3]
data[m-2]
data[m-1]
Memory
rsv[15:8]
rsv[7:0]
data[m]
data[1]
data[2]
6Eh
10h
Preliminary
status[23:16]
status[31:24]
status[15:8]
status[7:0]
crc[31:24]
crc[23:16]
High Byte
Low Byte
crc[15:8]
crc[7:0]
After reception is enabled, packets which are not
filtered out will be written into the circular receive buffer.
Any packet which does not meet the necessary filter
criteria will be discarded and the host controller will not
have any means of identifying that a packet was thrown
away. When a packet is accepted and completely
written into the buffer, the EPKTCNT register will incre-
ment, the EIR.PKTIF bit will be set, an interrupt will be
generated (if enabled) and the Hardware Write Pointer,
ERXWRPT, will automatically advance.
7.2.2
Figure 7-3 shows the layout of a received packet. The
packets are preceded by a six-byte header which
contains a Next Packet Pointer, in addition to a receive
status vector which contains receive statistics, includ-
ing the packet’s size. This receive status vector is
shown in Table 7-3.
If the last byte in the packet ends on an odd value
address, the hardware will automatically add a padding
byte when advancing the Hardware Write Pointer. As
such, all packets will start on an even boundary.
Description
RECEIVE PACKET LAYOUT
End of the Previous Packet
Next Packet Pointer
Receive Status Vector
Packet Data: Destination Address,
Source Address, Type/Length, Data,
Padding, CRC
Byte Skipped to Ensure
Even Buffer Address
Start of the Next Packet
ENC28J60
DS39662C-page 43