LTC4269CDKD-1#PBF Linear Technology, LTC4269CDKD-1#PBF Datasheet - Page 15

IC PD/OPTO FLYBACK CTRLR 32-DFN

LTC4269CDKD-1#PBF

Manufacturer Part Number
LTC4269CDKD-1#PBF
Description
IC PD/OPTO FLYBACK CTRLR 32-DFN
Manufacturer
Linear Technology
Type
Power Over Ethernet (PoE)r
Datasheet

Specifications of LTC4269CDKD-1#PBF

Applications
Power Interface Switch for Power Over Ethernet (PoE) Devices
Voltage - Supply
14 V ~ 16 V
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
32-DFN
Current - Supply
1.35mA
Interface
IEEE 802.3af
Controller Type
Powered Device Interface Controller (PD)
Input Voltage
60V
Supply Current
6.4mA
Digital Ic Case Style
DFN
No. Of Pins
32
Duty Cycle (%)
88%
Frequency
100kHz
Operating Temperature Range
0°C To +70°C
Msl
MSL 1 - Unlimited
Rohs Compliant
Yes
Operating Temperature (max)
70C
Operating Temperature (min)
0C
Pin Count
32
Mounting
Surface Mount
Package Type
DFN EP
Case Length
7mm
Screening Level
Commercial
Lead Free Status / RoHS Status
Lead free / RoHS Compliant

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Company:
Bonase Electronics (HK) Co., Limited Bonase Electronics (HK) Co., Limited
Part Number:
LTC4269CDKD-1#PBF
Manufacturer:
VOLTRONIC
Quantity:
2 140
Price:
APPLICATIONS INFORMATION
PSE
DETECTION V1
DETECTION V1
DETECTION V2
DETECTION V2
40mA
R
Figure 4. V
as a Result of 2-Event Classifi cation
INRUSH = 100mA
I
LOAD
–10
–20
–30
–40
–50
CLASS
I
50
40
30
20
10
50
40
30
20
10
IN
=
V
R
PORTN
1st CLASS
1st CLASS
LOAD
dV
1st MARK 2nd MARK
1st MARK 2nd MARK
dt
R
V
=
CLASS
NEG
2nd CLASS
2nd CLASS
PORTN
LTC4269-1
INRUSH
INRUSH
, T2P and PD Current
C1
OFF
V
PORTP
V
T2P
NEG
R
CLASS
ON
ON
= 30.9Ω
TRACKS
= R
V
OFF
OFF
PORTN
LOAD, I
LOAD
TIME
TIME
TIME
C1
42691 F04
C1
LOAD
R
LOAD
SIGNATURE CORRUPT DURING MARK
As a member of the IEEE 802.3at working group, Linear
Technology noted that it is possible for a Type 2 PD to
receive a false indication of a 2-event classifi cation if a PSE
port is pre-charged to a voltage above the detection voltage
range before the fi rst detection cycle. The IEEE working
group modifi ed the standard to prevent this possibility by
requiring a Type 2 PD to corrupt the signature resistance
during the mark event, alerting the PSE not to apply power.
The LTC4269-1 conforms to this standard by corrupting
the signature resistance. This also discharges the port
before the PSE begins the next detection cycle.
PD STABILITY DURING CLASSIFICATION
Classifi cation presents a challenging stability problem due
to the wide range of possible classifi cation load current.
The onset of the classifi cation load current introduces a
voltage drop across the cable and increases the forward
voltage of the input diode bridge. This may cause the PD
to oscillate between detection and classifi cation with the
onset and removal of the classifi cation load current.
The LTC4269-1 prevents this oscillation by introducing a
voltage hysteresis window between the detection and clas-
sifi cation ranges. The hysteresis window accommodates
the voltage changes a PD encounters at the onset of the
classifi cation load current, thus providing a trouble-free
transition between detection and classifi cation modes.
The LTC4269-1 also maintains a positive I-V slope through-
out the classifi cation range up to the on-voltage. In the
event a PSE overshoots beyond the classifi cation voltage
range, the available load current aids in returning the PD
back into the classifi cation voltage range. (The PD input
may otherwise be “trapped” by a reverse-biased diode
bridge and the voltage held by the 0.1μF capacitor).
INRUSH CURRENT
Once the PSE detects and optionally classifi es the PD,
the PSE then applies powers on the PD. When the
LTC4269-1 input voltage rises above the on-voltage
threshold, LTC4269-1 connects V
the internal power MOSFET.
NEG
LTC4269-1
to V
PORTN
through
15
42691fb

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