# LTC4269CDKD-1#PBF Linear Technology, LTC4269CDKD-1#PBF Datasheet - Page 26

#### LTC4269CDKD-1#PBF

Manufacturer Part Number

LTC4269CDKD-1#PBF

Description

IC PD/OPTO FLYBACK CTRLR 32-DFN

Manufacturer

Linear Technology

Type

Power Over Ethernet (PoE)r

Datasheet

1.LTC4269IDKD-1PBF.pdf
(44 pages)

#### Specifications of LTC4269CDKD-1#PBF

Applications

Power Interface Switch for Power Over Ethernet (PoE) Devices

Voltage - Supply

14 V ~ 16 V

Operating Temperature

0°C ~ 70°C

Mounting Type

Surface Mount

Package / Case

32-DFN

Current - Supply

1.35mA

Interface

IEEE 802.3af

Controller Type

Powered Device Interface Controller (PD)

Input Voltage

60V

Supply Current

6.4mA

Digital Ic Case Style

DFN

No. Of Pins

32

Duty Cycle (%)

88%

Frequency

100kHz

Operating Temperature Range

0Â°C To +70Â°C

Msl

MSL 1 - Unlimited

Rohs Compliant

Yes

Operating Temperature (max)

70C

Operating Temperature (min)

0C

Pin Count

32

Mounting

Surface Mount

Package Type

DFN EP

Case Length

7mm

Screening Level

Commercial

Lead Free Status / RoHS Status

Lead free / RoHS Compliant

APPLICATIONS INFORMATION

LTC4269-1

A ﬁ nal note—the susceptibility of the system to bistable

behavior is somewhat a function of the load current/

voltage characteristics. A load with resistive—i.e., I = V/R

behavior—is the most apt to be bistable. Capacitive loads

that exhibit I = V

Secondary Leakage Inductance

Leakage inductance on the secondary forms an inductive

divider on the transformer secondary, reducing the size

of the ﬂ yback pulse. This increases the output voltage

target by a similar percentage. Note that unlike leakage

spike behavior, this phenomenon is independent of load.

Since the secondary leakage inductance is a constant

percentage of mutual inductance (within manufacturing

variations), the solution is to adjust the feedback resistive

divider ratio to compensate.

Winding Resistance Effects

Primary or secondary winding resistance acts to reduce

overall efﬁ ciency (P

increases effective output impedance, degrading load regu-

lation. Load compensation can mitigate this to some extent

but a good design keeps parasitic resistances low.

Biﬁ lar Winding

A biﬁ lar, or similar winding, is a good way to minimize

troublesome leakage inductances. Biﬁ lar windings also

improve coupling coefﬁ cients, and thus improve cross

regulation in multiple winding transformers. However,

tight coupling usually increases primary-to-secondary

capacitance and limits the primary-to-secondary

breakdown voltage, so is not always practical.

Primary Inductance

The transformer primary inductance, L

based on the peak-to-peak ripple current ratio (X) in the

transformer relative to its maximum value. As a general

rule, keep X in the range of 20% to 40% (i.e., X = 0.2 to

0.4). Higher values of ripple will increase conduction losses,

while lower values will require larger cores.

26

2

/R behavior are less susceptible.

OUT

/P

IN

). Secondary winding resistance

P

,

is selected

Ripple current and percentage ripple is largest at minimum

duty cycle; in other words, at the highest input voltage.

L

where:

Using common high power PoE values, a 48V (41V < V

< 57V) to 5V/5.3A converter with 90% efﬁ ciency, P

26.5W and P

= 200kHz:

Optimization might show that a more efﬁ cient solution

is obtained at higher peak current but lower inductance

and the associated winding series resistance. A simple

spreadsheet program is useful for looking at trade-offs.

Transformer Core Selection

Once L

efﬁ ciency converters use ferrite cores to minimize core

loss. Actual core loss is independent of core size for a ﬁ xed

inductance, but decreases as inductance increases. Since

increased inductance is accomplished through more turns

of wire, copper losses increase. Thus, transformer design

balances core and copper losses. Remember that increased

winding resistance will degrade cross regulation and

increase the amount of load compensation required.

The main design goals for core selection are reducing

copper losses and preventing saturation. Ferrite core

material saturates hard, rapidly reducing inductance

when the peak design current is exceeded. This results

L

P

P

f

DC

X

DC

L

is calculated from the following equation.

OSC

=

MAX

P

(

MIN

MIN

=

V

P

f

is the oscillator frequency

IN(MAX)

OSC

is known, the type of transformer is selected. High

200kHz • 0.4 • 26.5W

is ripple current ratio at maximum input voltage

is the DC at maximum input voltage

=

(

• X

1+

57V • 0.412

IN

MAX

N • V

• DC

= 29.5W. Using X = 0.4 N = 1/8 and f

V

1

• P

MIN

IN(MAX)

OUT

IN

)

2

)

2

=

=

(

V

1+

= 260µH

IN(MAX)

f

OSC

8

1

1

•

• X

57

5

• DC

MAX

= 41.2%

MIN

• P

OUT

)

2

• Eff

42691fb

OUT

OSC

IN

=