UJA1075TW/3V3/WD,1 NXP Semiconductors, UJA1075TW/3V3/WD,1 Datasheet - Page 40

• Manufacturer Part Number: UJA1075TW/3V3/WD,1
• Description: IC SBC CAN/LIN HS 3.3V 32HTSSOP
• Manufacturer: NXP Semiconductors

Specifications of UJA1075TW/3V3/WD,1

• Controller Type: System Basis Chip
• Interface: CAN, LIN
• Voltage - Supply: 4.5 V ~ 28 V
• Current - Supply: 83µA
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Package / Case: 32-TSSOP Exposed Pad, 32-eTSSOP, 32-HTSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

NXP Semiconductors
10. Dynamic characteristics
Table 11.
T
are defined with respect to ground; positive currents flow in the IC; typical values are given at V
specified.
UJA1075_2
Product data sheet
Symbol
Voltage source; pin V1
t
t
Voltage source; pin V2
t
Serial peripheral interface timing; pins SCSN, SCK, SDI and SDO
t
t
t
t
t
t
t
t
t
Reset output; pin RSTN
t
t
t
Watchdog off input; pin WDOFF
t
Wake input; pin WAKE1, WAKE2
t
t
CAN transceiver timing; pins CANH, CANL, TXDC and RXDC
t
d(uvd)
det(CL)L
d(uvd)
cy(clk)
SPILEAD
SPILAG
clk(H)
clk(L)
su(D)
h(D)
v(Q)
WH(S)
w(rst)
det(CL)L
fltr
fltr
wake
d(po)
d(TXDCH-RXDCH)
vj
=
−
40 °C to +150
Dynamic characteristics
Parameter
undervoltage detection
delay time
LOW-level clamping
detection time
undervoltage detection
delay time
clock cycle time
SPI enable lead time
SPI enable lag time
clock HIGH time
clock LOW time
data input set-up time
data input hold time
data output valid time
chip select pulse width HIGH V
reset pulse width
LOW-level clamping
detection time
filter time
filter time
wake-up time
power-on delay time
delay time from TXDC HIGH
to RXDC HIGH
°
C; V
BAT
= 4.5 V to 28 V; V
All information provided in this document is subject to legal disclaimers.
BAT
V
V
V
V
V
V
pin SDO; V
Conditions
V
V
V
when SPI select falls
when SPI select rises
V
C
long; I
short; R
RSTN driven HIGH internally but RSTN
remains LOW
50 % V
V
R
C
f
TXDC
V1
V1
V2
V1
V1
V1
V1
V1
V1
V1
V1
V2
L
(CANH-CANL)
(CANH-CANL)
> V
Rev. 02 — 27 May 2010
= 100 pF
falling; dV
< 0.9V
falling, dV
= 2.97 V to 5.5 V
= 2.97 V to 5.5 V; clock is LOW
= 2.97 V to 5.5 V; clock is LOW
= 2.97 V to 5.5 V
= 2.97 V to 5.5 V
= 2.97 V to 5.5 V
= 2.97 V to 5.5 V
= 2.97 V to 5.5 V
= 4.5 V to 5.5 V
= 250 kHz
V1
pu(RSTN)
TXDC
pu(RSTN)
; V
BAT
O(V1)nom
V1
to 50 % V
= 60 Ω
= 100 pF; C
= 2.97 V to 5.5 V
V1
V2
< 100 μA; no pull-up
> V
/dt = 0.1 V/μs
/dt = 0.1 V/us
= 900 Ω to 1100 Ω
V2
; V1 active
; R
RXDC
LIN
High-speed CAN/LIN core system basis chip
RXDC
= 500
= 15 pF
Ω
; R
(CANH- CANL)
160
7
10
113
Min
7
95
7
320
110
140
160
0
80
-
20
20
3.6
95
0.9
60
BAT
= 45
= 14 V; unless otherwise
Ω
Typ
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
UJA1075
© NXP B.V. 2010. All rights reserved.
to 65
-
-
5
140
18
40
278
Max
23
140
23
-
-
-
-
-
110
-
25
2.3
235
Ω
; all voltages
40 of 53
Unit
μs
ms
μs
ns
ns
ns
ns
ns
ns
ns
ns
ns
ms
ms
ms
μs
ms
μs
μs
ns