UJA1075TW/3V3 NXP [NXP Semiconductors], UJA1075TW/3V3 Datasheet

UJA1075TW/3V3

Manufacturer Part Number

UJA1075TW/3V3

Description

High-speed CAN/LIN core system basis chip

Manufacturer

NXP [NXP Semiconductors]

Datasheet

1.UJA1075TW3V3.pdf (53 pages)

Available stocks

Company

Part Number

Manufacturer

Quantity

Price

Company:

Meier Automation Equipment Co., Limited

Part Number:

UJA1075TW/3V3/WD:1

Manufacturer:

NXP/恩智浦

Quantity:

20 000

Current page: 1 of 53
Download datasheet (388Kb)

1. General description

The UJA1075 core System Basis Chip (SBC) replaces the basic discrete components

commonly found in Electronic Control Units (ECU) with a high-speed Controller Area

Network (CAN) and a Local Interconnect Network (LIN) interface.

The UJA1075 supports the networking applications used to control power and sensor

peripherals by using a high-speed CAN as the main network interface and the LIN

interface as a local sub-bus.

The core SBC contains the following integrated devices:

In addition to the advantages gained from integrating these common ECU functions in a

single package, the core SBC offers an intelligent combination of system-specific

functions such as:

The UJA1075 is designed to be used in combination with a microcontroller that

incorporates a CAN controller. The SBC ensures that the microcontroller always starts up

in a controlled manner.

•

UJA1075

High-speed CAN/LIN core system basis chip

Rev. 02 — 27 May 2010

High-speed CAN transceiver, inter-operable and downward compatible with CAN

transceiver TJA1042, and compatible with the ISO 11898-2 and ISO 11898-5

standards

LIN transceiver compliant with LIN 2.1, LIN 2.0 and SAE J2602, and compatible with

LIN 1.3

Advanced independent watchdog (UJA1075/xx/WD versions)

250 mA voltage regulator for supplying a microcontroller; extendable with external

PNP transistor for increased current capability and dissipation distribution

Separate voltage regulator for supplying the on-board CAN transceiver

Serial Peripheral Interface (SPI) (full duplex)

2 local wake-up input ports

Limp home output port

Advanced low-power concept

Safe and controlled system start-up behavior

Detailed status reporting on system and sub-system levels

Product data sheet

Related parts for UJA1075TW/3V3

UJA1075TW/3V3 Summary of contents

Page 1

UJA1075 High-speed CAN/LIN core system basis chip Rev. 02 — 27 May 2010 1. General description The UJA1075 core System Basis Chip (SBC) replaces the basic discrete components commonly found in Electronic Control Units (ECU) with a high-speed Controller Area ...

Page 2

NXP Semiconductors 2. Features and benefits 2.1 General Contains a full set of CAN and LIN ECU functions: CAN transceiver and LIN transceiver Scalable 3 voltage regulator delivering up to 250 mA for a microcontroller and ...

Page 3

NXP Semiconductors Output signal (WBIAS) to bias the wake pins, selectable sampling time Standby mode with very low standby current and full wake-up capability; V1 active to maintain supply to the microcontroller Sleep mode ...

Page 4

... NXP Semiconductors 3. Ordering information Table 1. Ordering information [1] Type number Package Name UJA1075TW/5V0/WD HTSSOP32 UJA1075TW/3V3/WD UJA1075TW/5V0 UJA1075TW/3V3 [1] UJA1075TW/5V0xx versions contain regulator (V1); UJA1075TW/3V3xx versions contain a 3.3 V regulator (V1); WD versions contain a watchdog. 4. Block diagram BAT GND SCK SDI SDO SCSN WAKE1 WAKE WAKE2 WDOFF EN ...

Page 5

NXP Semiconductors 5. Pinning information 5.1 Pinning Fig 2. 5.2 Pin description Table 2. Symbol i.c. i.c. TXDL V1 RXDL RSTN INTN EN SDI SDO SCK SCSN TXDC RXDC TEST1 WDOFF LIMP UJA1075_2 Product data sheet i.c. 1 i.c. 2 ...

Page 6

NXP Semiconductors Table 2. Symbol WAKE1 WAKE2 V2 CANH CANL GND SPLIT LIN DLIN i.c. WBIAS VEXCC TEST2 VEXCTRL BAT The exposed die pad at the bottom of the package allows for better heat dissipation from the SBC via the ...

Page 7

NXP Semiconductors 6.1 System Controller 6.1.1 Introduction The system controller manages register configuration and controls the internal functions of the SBC. Detailed device status information is collected and presented to the microcontroller. The system controller also provides the reset and ...

Page 8

NXP Semiconductors V below BAT power-off threshold V th(det)poff (from all modes) V below BAT power-on threshold V th(det)pon CAN/LIN: Active/Lowpower successful watchdog trigger Fig 3. UJA1075 system controller UJA1075_2 Product data sheet Overtemp V1: OFF V2: OFF limp home ...

Page 9

NXP Semiconductors 6.1.2 Off mode The SBC switches to Off mode from all other modes if the battery supply drops below the power-off detection threshold (V and the bus systems are in a high-resistive state. The CAN bus pins are ...

Page 10

NXP Semiconductors • The chip temperature rises above the OTP activation threshold, T SBC to switch to Overtemp mode 6.1.5 Sleep mode Sleep mode is selected from Standby mode or Normal mode by setting bits MC in the Mode_Control register ...

Page 11

NXP Semiconductors SCS SCK 01 sampled SDI X SDO X floating Fig 4. SPI timing protocol 6.2.2 Register map The first three bits (A2, A1 and A0) of the message header define the register address. The fourth bit (RO) defines ...

Page 12

NXP Semiconductors 6.2.3 WD_and_Status register Table 4. WD_and_Status register Bit Symbol Access Power-on default 15:13 A2, A1 000 WMC R/W 0 [1] 10:8 NWP R/W 100 7 WOS/SWR R V1S R ...

Page 13

NXP Semiconductors 6.2.4 Mode_Control register Table 5. Mode_Control register Bit Symbol Access Power-on default 15:13 A2, A1 001 12 RO R/W 0 11:10 MC R/W 00 [1] 9 LHWC R/W 1 [2] 8 LHC R ENC ...

Page 14

NXP Semiconductors 6.2.5 Int_Control register Table 6. Int_Control register Bit Symbol Access Power-on default 15:13 A2, A1 010 V1UIE R V2UIE R STBCL R reserved R 0 ...

Page 15

NXP Semiconductors Table 6. Int_Control register Bit Symbol Access Power-on default 2 RTHC R WSE1 R WSE2 R/W 0 UJA1075_2 Product data sheet High-speed CAN/LIN core system basis chip Description reset threshold control 0: The reset ...

Page 16

NXP Semiconductors 6.2.6 Int_Status register [1] Table 7. Int_Status register Bit Symbol Access Power-on default 15:13 A2, A1 011 V1UI R V2UI R LWI R reserved R ...

Page 17

NXP Semiconductors 6.4 Watchdog (UJA1075/xx/WD versions) Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is programmed via the NWP control bits in the WD_and_Status register (see default watchdog period is 128 ms. A watchdog trigger event ...

Page 18

NXP Semiconductors • the SBC is in Standby mode and bit WMC = 0 or • the SBC is in Normal mode and bit WMC = 1 6.4.3 Watchdog Off behavior The watchdog is disabled in this state. The watchdog ...

Page 19

NXP Semiconductors The reset pulse width (t generated undervoltage event (see (V > V BAT selected by connecting a 900 Ω ±10 % resistor between pins RSTN and V1 resistor is not connected, the reset ...

Page 20

NXP Semiconductors 6.6 Power supplies 6.6.1 Battery pin (BAT) The SBC contains a single supply pin, BAT. An external diode is needed in series to protect the device against negative voltages. The operating range is from 4 ...

Page 21

NXP Semiconductors current current Fig 7. Figure 7 current of 250 mA with PDC = 0. Any additional load current requirement will be supplied by the PNP transistor its current limit. If the load current continues to rise, ...

Page 22

NXP Semiconductors For short-circuit protection, a resistor needs to be connected between pins V1 and VEXCC to allow the current to be monitored. This resistor limits the current delivered by the external transistor. If the voltage difference between pins VEXCC ...

Page 23

NXP Semiconductors • the SBC is in Normal mode ( 11) • the transceiver is enabled (bit STBCC = 0; see and • enabled and its output voltage is above its undervoltage threshold ...

Page 24

NXP Semiconductors 6.7.2 Split circuit Pin SPLIT provides a DC stabilized voltage of 0.5V only. Pin SPLIT is floating in CAN Lowpower and Off modes. The V used to stabilize the recessive common-mode voltage by connecting pin SPLIT to the ...

Page 25

NXP Semiconductors 6.8.1 LIN operating modes 6.8.1.1 Active mode The LIN transceiver will be in Active mode when: • the SBC is in Normal mode ( 11) and • the transceiver is enabled (STBCL = 0; see ...

Page 26

NXP Semiconductors edge on pin TXDL. If the pin remains LOW for longer than the TXDL dominant time-out time (t to(dom)TXDL The timer is reset by a positive edge on the TXDL pin. 6.9 Local wake-up input The SBC provides ...

Page 27

NXP Semiconductors Fig 12. Typical application for cyclic sampling of wake-up signals 6.10 Interrupt output Pin INTN is an active-LOW, open-drain interrupt output driven LOW when at least one interrupt is pending. An interrupt can be cleared by ...

Page 28

NXP Semiconductors 7. Limiting values Table 8. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V voltage on pin reverse current from R(V1-BAT) pin V1 to pin BAT I current on ...

Page 29

NXP Semiconductors Table 8. Limiting values …continued In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter T ambient amb temperature [1] A reverse diode connected between V1 (anode) and BAT (cathode) limits the voltage drop voltage from ...

Page 30

NXP Semiconductors 8. Thermal characteristics Fig 13. HTSSOP PCB UJA1075_2 Product data sheet PCB copper area: (bottom layer PCB copper area: (bottom layer measurements: board finish thickness 1.6 mm ±10 %, double-layer Layout conditions ...

Page 31

NXP Semiconductors R (K/W) Fig 14. HTSSOP32 thermal resistance junction to ambient as a function of PCB copper Table 9. Symbol R th(j-a) [1] According to JEDEC JESD51-2 and JESD51-3 at natural convection on 1s board. [2] According to JEDEC ...

Page 32

NXP Semiconductors 9. Static characteristics Table 10. Static characteristics − ° °C to +150 4 BAT are defined with respect to ground; positive currents flow in the IC; ...