UJA1075TW/3V3 NXP [NXP Semiconductors], UJA1075TW/3V3 Datasheet - Page 8

• Manufacturer Part Number: UJA1075TW/3V3
• Description: High-speed CAN/LIN core system basis chip
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
UJA1075_2
Product data sheet
Fig 3.
power-on threshold V
power-off threshold V
UJA1075 system controller
(from all modes)
V
BAT
V
successful
watchdog
BAT
trigger
below
below
th(det)pon
th(det)poff
CAN/LIN: Active/Lowpower
watchdog: Window/
CAN/LIN: Off and
high resistance
watchdog: OFF
V2: ON/OFF
Timeout/Off
INTN: HIGH
MC = 1x
Normal
V1: OFF
V2: OFF
V1: ON
reset event or
Off
MC = 00
All information provided in this document is subject to legal disclaimers.
watchdog overflow or
V1 undervoltage
Rev. 02 — 27 May 2010
power-on threshold V
limp home = LOW (active)
MC = 10 or MC = 11
CAN/LIN: Off and
watchdog: OFF
high resistance
V
one wake-up enabled and
Overtemp
BAT
V1: OFF
V2: OFF
no wake-up pending
INTN = HIGH and
CAN/LIN: Lowpower/Off
watchdog: Timeout/Off
above
MC = 01 and
High-speed CAN/LIN core system basis chip
Standby
th(det)pon
V2: OFF
MC = 00
V1: ON
OTP release threshold T
wake-up event if enabled
chip temperature below
OTP activatrion threshold T
watchdog
trigger
chip temperature above
th(rel)otp
one wake-up enabled and
CAN/LIN: Lowpower/Off
from Standby or Normal
no wake-up pending
INTN = HIGH and
watchdog: OFF
RSTN: LOW
MC = 01 and
UJA1075
V1: OFF
V2: OFF
MC = 01
© NXP B.V. 2010. All rights reserved.
Sleep
th(act)otp
015aaa073
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