uja1075 NXP Semiconductors, uja1075 Datasheet
uja1075
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uja1075 Summary of contents
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... Safe and controlled system start-up behavior • Detailed status reporting on system and sub-system levels The UJA1075 is designed to be used in combination with a microcontroller that incorporates a CAN controller. The SBC ensures that the microcontroller always starts controlled manner. Product data sheet ...
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... Wake pins: WAKE1 and WAKE2 inputs can be switched off to reduce current flow UJA1075_2 Product data sheet High-speed CAN/LIN core system basis chip All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 © NXP B.V. 2010. All rights reserved ...
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... Product data sheet High-speed CAN/LIN core system basis chip voltages down to 4.5 V (e.g. during cranking), in accordance BAT voltages down to 5.5 V (e.g. during cranking) in accordance BAT All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 3. Ordering information Table 1. Ordering information [1] Type number Package Name UJA1075TW/5V0/WD HTSSOP32 UJA1075TW/3V3/WD UJA1075TW/5V0 UJA1075TW/3V3 [1] UJA1075TW/5V0xx versions contain regulator (V1); UJA1075TW/3V3xx versions contain a 3.3 V regulator (V1); WD versions contain a watchdog. 4. Block diagram BAT GND SCK SDI SDO SCSN WAKE1 WAKE WAKE2 WDOFF EN ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 High-speed CAN/LIN core system basis chip 32 BAT 31 VEXCTRL 30 TEST2 29 VEXCC 28 WBIAS 27 i.c. 26 DLIN 25 LIN UJA1075 24 SPLIT 23 GND 22 CANL 21 CANH WAKE2 18 WAKE1 17 LIMP 015aaa119 UJA1075 © NXP B.V. 2010. All rights reserved ...
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... IC and can be left floating, or can be connected to GND. 6. Functional description The UJA1075 combines the functionality of a high-speed CAN transceiver, a LIN transceiver, two voltage regulators and a watchdog (UJA1075/xx/WD versions single, dedicated chip. It handles the power-up and power-down functionality of the ECU and ensures advanced system reliability ...
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... UJA1075_2 Product data sheet High-speed CAN/LIN core system basis chip All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 Figure 3. These modes are discussed in © NXP B.V. 2010. All rights reserved ...
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... V th(det)poff (from all modes) V below BAT power-on threshold V th(det)pon CAN/LIN: Active/Lowpower successful watchdog trigger Fig 3. UJA1075 system controller UJA1075_2 Product data sheet Overtemp V1: OFF V2: OFF limp home = LOW (active) CAN/LIN: Off and high resistance watchdog: OFF Off V1: OFF V2: OFF ...
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... Rev. 02 — 27 May 2010 High-speed CAN/LIN core system basis chip ). In Off mode, the voltage regulators are disabled and Table 11). Table 6) with bus wake-up (Table 4). 6.1.3; the SBC will enter Standby mode) UJA1075 ), th(det)pon ) th(det)pon , causing the th(act)otp © NXP B.V. 2010. All rights reserved ...
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... The watchdog is off and the reset pin is LOW. Section 6.5.1 and Table Figure 4). All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 High-speed CAN/LIN core system basis chip th(act)otp Section 6.7.1 Section 6.5.1) system reset. The value of 11). © NXP B.V. 2010. All rights reserved. ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 High-speed CAN/LIN core system basis chip LSB 12 01 LSB Read/Write access bits 11... 0 WD_and_Status register Mode_Control register Int_Control register Int_Status register UJA1075 X floating mce634 © NXP B.V. 2010. All rights reserved ...
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... WAKE1 input voltage below switching threshold (V 1: WAKE1 input voltage above switching threshold (V wake-up 2 status 0: WAKE2 input voltage below switching threshold (V 1: WAKE2 input voltage above switching threshold (V All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 ) th(sw) ) th(sw) ) th(sw) ...
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... V1 threshold current for activating the external PNP transistor; load current rising mA; V1 threshold current for deactivating the external th(act)PNP PNP transistor; load current falling; I All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 = 50 mA; see Figure 7 th(deact)PNP = 15 mA; see Figure 7 th(deact)PNP © ...
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... CAN is in Lowpower mode with bus wake-up detection enabled, regardless of the SBC mode (MC = xx). CAN wake-up interrupts can be requested. All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 . BAT © NXP B.V. 2010. All rights reserved ...
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... WAKE1 is synchronized with WBIAS (sample rate controlled by WBC) WAKE2 sample enable 0: sampling continuously 1: sampling of WAKE1 is synchronized with WBIAS (sample rate controlled by WBC) All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 © NXP B.V. 2010. All rights reserved ...
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... CAN wake-up interrupt 0: no CAN wake-up interrupt pending 1: CAN wake-up interrupt pending All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 © NXP B.V. 2010. All rights reserved ...
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... NXP Semiconductors 6.4 Watchdog (UJA1075/xx/WD versions) Three watchdog modes are supported: Window, Timeout and Off. The watchdog period is programmed via the NWP control bits in the WD_and_Status register (see default watchdog period is 128 ms. A watchdog trigger event is any write access to the WD_and_Status register. When the watchdog is triggered, the watchdog timer is reset ...
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... SBC leaves Overtemp mode (reset pulse length selected via external pull-up resistor on RSTN pin) A watchdog overflow in Timeout mode requests a cyclic interrupt (CI not already pending. The UJA1075 provides three signals for dealing with reset events: • RSTN input/output for performing a global ECU system reset or forcing an external reset • ...
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... Rev. 02 — 27 May 2010 High-speed CAN/LIN core system basis chip Section 6.6. the SBC leaving Off ) modes. A short reset pulse is th(rel)otp Table 11). 5) via the SPI interface. Pin EN will be HIGH when NORMAL UJA1075 STANDBY 015aaa074 © NXP B.V. 2010. All rights reserved ...
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... Voltage regulator V1 is intended to supply the microcontroller, its periphery and additional transceivers supplied by pin BAT and delivers up to 250 (depending on the UJA1075 version). To prevent the device overheating at high ambient temperatures or high average currents, an external PNP transistor can be connected as illustrated in configuration, the power dissipation is distributed between the SBC and the PNP transistor ...
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... PNP current V1 and PNP currents at a fast ramping load current of 250 mA (PDC = 0) All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 High-speed CAN/LIN core system basis chip 215 th(deact)PNP (PDC = 0) © NXP B.V. 2010. All rights reserved. ...
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... V1. The alternative voltage source must be connected to pin V2. All internal functions (e.g. undervoltage protection) will work normally. 6.7 CAN transceiver The analog section of the UJA1075 CAN transceiver corresponds to that integrated into the TJA1042/TJA1043. The transceiver is designed for high-speed ( Mbit/s) CAN applications in the automotive industry, providing differential transmit and receive capability to a CAN protocol controller ...
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... CAN wake-up timing diagram All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 High-speed CAN/LIN core system basis chip Table 6) 6.6.3) Table 11). recessive t < ...
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... Pin TXDC has an internal pull-up towards V pin is left floating. 6.8 LIN transceiver The analog sections of the UJA1075 LIN transceiver is identical to that integrated into the TJA1021. The transceiver is the interface between the LIN master/slave protocol controller and the physical bus in a LIN primarily intended for in-vehicle sub-networks using baud rates from 1 kBd kBd and is LIN 2 ...
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... BAT Figure 1) - LIN recessive is represented by a HIGH Table 6). The LIN transceiver can be woken up remotely via pin LIN in wake(busdom)min All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 Table 6) and (see Table 11). to guarantee a safe, defined state if this V1 © ...
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... WAKEx pin Wake-up int shows typical circuit for implementing cyclic sampling of the wake-up inputs. All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 High-speed CAN/LIN core system basis chip Table 6). These bits can also be used to disable (Table 4) ...
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... WBIAS WAKE1 WAKE2 GND (Table 7). Clearing bits LWI and CWI in Standby mode only Section 6.1.6 “Overtemp All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 High-speed CAN/LIN core system basis chip PDTA144E biasing of switches sample of sample of WAKEx WAKEx mode” ...
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... TEST2; referenced to other reference pins any other pin MM any pin CDM corner pins any other pin All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 High-speed CAN/LIN core system basis chip Min −0.3 −0.3 − 0 −58 − ...
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... UJA1075_2 Product data sheet Conditions . The rating for T limits the allowable combinations of power dissipation (P) and ambient vj vj All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 High-speed CAN/LIN core system basis chip Min − × amb th(vj-a) © ...
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... Cu thickness on vias 0.025 mm. Optional heat sink top layer of 3.5 mm × will reduce thermal resistance (see All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 High-speed CAN/LIN core system basis chip optional heatsink top layer optional heatsink top layer optional heatsink top layer © ...
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... Parameter thermal resistance from junction to ambient All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 High-speed CAN/LIN core system basis chip PCB Cu heatsink area (cm Conditions single-layer board four-layer board UJA1075 015aaa138 Typ Unit [1] 78 K/W [2] 39 K/W © NXP B.V. 2010. All rights reserved. ...
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... V < V < BAT contributed by WAKEn pin edge detectors WIC1 = WIC2 = WAKE1 WAKE2 BAT All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 Ω Ω (CANH-CANL unless otherwise BAT Min Typ Max 4.5 - ...
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... V TXDC TXDC - - = BAT = 0 mA 4.5 - 4.25 - 200 - 5.9 - UJA1075 Ω Ω all voltages Max Unit μ μA 950 μA 1300 5 5.3 V 5.5 V 300 mV 7.5 V © NXP B.V. 2010. All rights reserved ...
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... 3.234 3.3 ≥ 560 pF LIN = 4 3.201 3.3 ≥ 220 pF LIN = 4 2.97 3 4.5 - 2.97 - 3.5 - 4.56 - 3.025 - −600 - - - - - = − 3.5 5.8 UJA1075 Ω Ω all voltages Max Unit 5.1 V 5.15 V 5.1 V 5.1 V 5.1 V 3.366 V 3.399 V 3.366 V Ω 3 4.75 V 3.135 V 3.75 V 4.9 V 3.234 V −250 mA 25 ...
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... Section 6.6.2 74 130 Section 6.6 240 - 4. 4 −250 - 0. 100 - 50 130 50 130 UJA1075 Ω Ω all voltages Max Unit 191 114 120 330 mV 5. 4. −100 mA 0. 900 ...
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... V1 −1500 - 4.9 - 200 - 0 - < BAT 100 - 1.6 - − 100 - 100 - −2 - UJA1075 Ω Ω all voltages Max Unit μA +5 −1 μA 5 −100 μ μA 540 0. 0 0.3 0. 900 −1 0 900 ...
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... V TXDC 2.75 3.5 0.5 1.5 − V −400 - CANL 1 TXDC − TXDC 0.5V −0.1 - −100 − −3 - UJA1075 Ω Ω all voltages Max Unit μ 0. 900 mV 25 kΩ −1 kΩ 4.5 V 2.25 V 400 mV 3.0 V +50 mV ...
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... 5 −5 - 0.3V 0.5V V2 0.45 × 0.5 × ≥ 1 MΩ − 100 - 4 12 − UJA1075 Ω Ω all voltages Max Unit 0.9 V 1.15 V 400 mV 28 kΩ kΩ μ 0.55 × μ 900 mV 25 kΩ ...
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... V V BAT BAT 0.05 × 0.15 × th(dom) BAT BAT - - - - - - 0.4 0.65 165 180 126 138 UJA1075 Ω Ω all voltages Max Unit μA 2 μA +10 μA 10 μ 0.4V V BAT 0.525 × BAT 0.175 × BAT ...
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... Ω R (CANH-CANL 100 pF; C (CANH-CANL) RXDC f = 250 kHz TXDC All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 Ω Ω Ω all voltages (CANH- CANL unless otherwise BAT Min Typ Max 7 ...
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... LSC = 0 BAT V = 0.41V th(rec)RX(min) BAT V = 0.275V th(dom)RX(min) BAT 7.6 V; LSC = 0 BAT All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 Ω Ω = 500 ; (CANH- CANL unless otherwise BAT Min Typ ...
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... C = 6.8 nF and illustrated in the LIN timing diagram in bus(rec)(max) All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 High-speed CAN/LIN core system basis chip Ω Ω = 500 ; LIN (CANH- CANL unless otherwise ...
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... TXDC CANL GND t d(TXDC-busrec) t d(busdom-RXDC) t d(TXDCH-RXDCH) All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 , but not more than t , after the start of the trig(wd)2 R CANH − R CANL C CANH − C CANL 015aaa079 0 d(busrec-RXDC) © NXP B.V. 2010. All rights reserved. ...
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... PD(RX)f PD(RX)r t PD(RX)r All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 High-speed CAN/LIN core system basis chip BAT DLIN R LIN SBC LIN C LIN GND 015aaa128 t bit V th(rec)RX(max) ...
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... Product data sheet T cy(clk clk(H) clk( su(D) h(D) MSB X MSB All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 High-speed CAN/LIN core system basis chip t t SPILAG WH(S) LSB X t v(Q) floating LSB 015aaa045 © NXP B.V. 2010. All rights reserved ...
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... Rev. 02 — 27 May 2010 High-speed CAN/LIN core system basis chip detail 8.3 0.75 0.65 1 0.2 0.1 7.9 0.50 EUROPEAN PROJECTION UJA1075 SOT549 θ θ 0.78 8 0.1 o 0.48 0 ISSUE DATE 03-04-07 05-11-02 © NXP B.V. 2010. All rights reserved ...
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... Solder bath specifications, including temperature and impurities UJA1075_2 Product data sheet High-speed CAN/LIN core system basis chip All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 © NXP B.V. 2010. All rights reserved ...
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... Volume (mm ) < 350 260 260 250 Figure 21. All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 High-speed CAN/LIN core system basis chip Figure 21) than a SnPb process, thus ≥ 350 220 220 350 to 2000 > 2000 260 260 250 ...
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... MSL limit, damage level temperature minimum peak temperature = minimum soldering temperature MSL: Moisture Sensitivity Level All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 High-speed CAN/LIN core system basis chip peak temperature © NXP B.V. 2010. All rights reserved. time 001aac844 ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 High-speed CAN/LIN core system basis chip Change notice Supersedes - UJA1075_1 , I ESD R(V1-BAT th(cntr)RX th(hys)RX OL for RSTN pin det(CL)L 11: parameters renamed to t wake(busdom)min - - UJA1075 for RSTN pin, , © NXP B.V. 2010. All rights reserved ...
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... All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 High-speed CAN/LIN core system basis chip © NXP B.V. 2010. All rights reserved ...
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... High-speed CAN/LIN core system basis chip 15.4 Trademarks Notice: All referenced brands, product names, service names and trademarks are the property of their respective owners. http://www.nxp.com salesaddresses@nxp.com All information provided in this document is subject to legal disclaimers. Rev. 02 — 27 May 2010 UJA1075 © NXP B.V. 2010. All rights reserved ...
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... Overtemp mode . . . . . . . . . . . . . . . . . . . . . . . 10 6.2 SPI . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10 6.2.1 Introduction 6.2.2 Register map . . . . . . . . . . . . . . . . . . . . . . . . . 11 6.2.3 WD_and_Status register 6.2.4 Mode_Control register . . . . . . . . . . . . . . . . . . 13 6.2.5 Int_Control register . . . . . . . . . . . . . . . . . . . . . 14 6.2.6 Int_Status register 6.3 On-chip oscillator . . . . . . . . . . . . . . . . . . . . . . 16 6.4 Watchdog (UJA1075/xx/WD versions 6.4.1 Watchdog Window behavior . . . . . . . . . . . . . . 17 6.4.2 Watchdog Timeout behavior . . . . . . . . . . . . . . 17 6.4.3 Watchdog Off behavior . . . . . . . . . . . . . . . . . . 18 6.5 System reset 6.5.1 RSTN pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 6.5.2 EN output . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.5.3 LIMP output . . . . . . . . . . . . . . . . . . . . . . . . . . 19 6.6 Power supplies . . . . . . . . . . . . . . . . . . . . . . . . 20 6.6.1 Battery pin (BAT ...