UJA1075TW/3V3 NXP [NXP Semiconductors], UJA1075TW/3V3 Datasheet - Page 14

• Manufacturer Part Number: UJA1075TW/3V3
• Description: High-speed CAN/LIN core system basis chip
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 6.
UJA1075_2
Product data sheet
Bit
15:13
12
11
10
9
8
7:6
5:4
3
Symbol
A2, A1, A0 R
RO
V1UIE
V2UIE
STBCL
reserved
WIC1
WIC2
STBCC
Int_Control register
6.2.5 Int_Control register
Access Power-on
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
default
010
0
0
0
0
0
00
00
0
All information provided in this document is subject to legal disclaimers.
Description
register address
access status
V1 undervoltage interrupt enable
V2 undervoltage interrupt enable
LIN standby control
wake-up interrupt 1 control
wake-up interrupt 2 control
CAN standby control
0: register set to read/write
1: register set to read only
0: V1 undervoltage warning interrupts cannot be requested
1: V1 undervoltage warning interrupts can be requested
0: V2 undervoltage warning interrupts cannot be requested
1: V2 undervoltage warning interrupts can be requested
0: When the SBC is in Normal mode (MC = 1x):
When the SBC is in Standby/Sleep mode (MC = 0x):
1: LIN is in Lowpower mode with bus wake-up detection enabled, regardless
of the SBC mode (MC = xx). LIN wake-up interrupts can be requested.
00: wake-up interrupt 1 disabled
01: wake-up interrupt 1 on rising edge
10: wake-up interrupt 1 on falling edge
11: wake-up interrupt 1 on both edges
00: wake-up interrupt 2 disabled
01: wake-up interrupt 2 on rising edge
10: wake-up interrupt 2 on falling edge
11: wake-up interrupt 2 on both edges
0: When the SBC is in Normal mode (MC = 1x):
When the SBC is in Standby/Sleep mode (MC = 0x):
1: CAN is in Lowpower mode with bus wake-up detection enabled,
regardless of the SBC mode (MC = xx). CAN wake-up interrupts can be
requested.
LIN is in Active mode. The wake-up flag (visible on RXDL) is cleared
regardless of the value of V
LIN is in Off mode. Bus wake-up detection is disabled. LIN wake-up
interrupts cannot be requested.
CAN is in Active mode. The wake-up flag (visible on RXDC) is cleared
regardless of V2 output voltage.
CAN is in Off mode. Bus wake-up detection is disabled. CAN wake-up
interrupts cannot be requested.
Rev. 02 — 27 May 2010
High-speed CAN/LIN core system basis chip
BAT
.
UJA1075
© NXP B.V. 2010. All rights reserved.
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