UJA1075TW/3V3 NXP [NXP Semiconductors], UJA1075TW/3V3 Datasheet - Page 16

• Manufacturer Part Number: UJA1075TW/3V3
• Description: High-speed CAN/LIN core system basis chip
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
Table 7.
[1]
UJA1075_2
Product data sheet
Bit
15:13
12
11
10
9
8
7
6
5
4
3
2:0
An interrupt can be cleared by writing 1 to the relevant bit in the Int_Status register.
Symbol
A2, A1, A0 R
RO
V1UI
V2UI
LWI
reserved
CI
WI1
POSI
WI2
CWI
reserved
Int_Status register
6.2.6 Int_Status register
6.3 On-chip oscillator
Access Power-on
R/W
R/W
R/W
R/W
R
R/W
R/W
R/W
R/W
R/W
R
The on-chip oscillator provides the timing reference for the on-chip watchdog and the
internal timers. The on-chip oscillator is supplied by an internal supply that is connected to
V
BAT
and is independent of V1/V2.
[1]
default
011
0
0
0
0
0
0
0
1
0
0
000
All information provided in this document is subject to legal disclaimers.
Description
register address
access status
V1 undervoltage interrupts
V2 undervoltage interrupts
LIN wake-up interrupt
cyclic interrupt
wake-up interrupt 1
power-on status interrupt
wake-up interrupt 2
CAN wake-up interrupt
0: register set to read/write
1: register set to read only
0: no V1 undervoltage warning interrupt pending
1: V1 undervoltage warning interrupt pending
0: no V2 undervoltage warning interrupt pending
1: V2 undervoltage warning interrupt pending
0: no LIN wake-up interrupt pending
1: LIN wake-up interrupt pending
0: no cyclic interrupt pending
1: cyclic interrupt pending
0: no wake-up interrupt 1 pending
1: wake-up interrupt 1 pending
0: no power-on interrupt pending
1: power-on interrupt pending
0: no wake-up interrupt 2 pending
1: wake-up interrupt 2 pending
0: no CAN wake-up interrupt pending
1: CAN wake-up interrupt pending
Rev. 02 — 27 May 2010
High-speed CAN/LIN core system basis chip
UJA1075
© NXP B.V. 2010. All rights reserved.
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