UJA1075TW/3V3 NXP [NXP Semiconductors], UJA1075TW/3V3 Datasheet - Page 43

• Manufacturer Part Number: UJA1075TW/3V3
• Description: High-speed CAN/LIN core system basis chip
• Manufacturer: NXP [NXP Semiconductors]

NXP Semiconductors
[7]
UJA1075_2
Product data sheet
The watchdog will be reset if it is in window mode and is triggered at least t
watchdog period (or in the second half of the watchdog period). A system reset will be performed if the watchdog is triggered more than
t
trig(wd)2
after the start of the watchdog period (watchdog overflows).
Fig 15. Timing test circuit for CAN transceiver
Fig 16. CAN transceiver timing diagram
TXDC
CANH
CANL
V
RXDC
t
t
d(TXDCL-RXDCL)
O(dif)bus
d(TXDC-busdom)
All information provided in this document is subject to legal disclaimers.
C RXDC
Rev. 02 — 27 May 2010
RXDC
TXDC
t
d(busdom-RXDC)
SBC
GND
BAT
t
d(TXDCH-RXDCH)
t
trig(wd)1
d(TXDC-busrec)
High-speed CAN/LIN core system basis chip
CANH
CANL
, but not more than t
R CANH − R CANL
015aaa079
trig(wd)2
0.9 V
0.5 V
, after the start of the
C CANH − C CANL
UJA1075
© NXP B.V. 2010. All rights reserved.
t
d(busrec-RXDC)
HIGH
LOW
dominant
recessive
HIGH
LOW
015aaa151
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