Z87L0116ASC1937 Zilog, Z87L0116ASC1937 Datasheet - Page 33

• Manufacturer Part Number: Z87L0116ASC1937
• Description: IC FHSS PHONE CTRL 144-VQFP
• Manufacturer: Zilog

Specifications of Z87L0116ASC1937

• Controller Type: Phone Controller
• Interface: Bus
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 55mA
• Operating Temperature: -20°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Zilog
REGISTER DESCRIPTION
The Z87001 DSP core processor has four banks of eight
registers mapped in the core processor’s “external regis-
ter” space, as summarized in the following table.
DS96WRL0800
Bank 3
Bank 2
Bank 1
Bank 0
BANK ADDRESS
EXT0
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
EXT0
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
EXT0
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
EXT0
EXT1
EXT2
EXT3
EXT4
EXT5
EXT6
EXT7
CONFIG1
CONFIG2
SSPSTATE
SSPSTATUS
GPIO0DIR
GPIO0DATA
GPIO1DIR
GPIO1DATA
VP_INOUT
RX_CONTROL
BIAS_ERROR
RSSI
CORE_BIAS
MOD_PWR_CTRL
DEMOD_PWR_CTRL
RFTX_PWR_CTRL
RATE_BUF_ADDR
RATE_BUF_DATA
BIT_SYNC
RESERVED
RESERVED
RESERVED
CONTROL
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
RESERVED
INT_SYM_ERR0
RFRX_PWR_CTRL
REGISTER
Table 10. Register Summary
Frame Counter, Handset/Base,
Sync Search control, Frame
Search control, Hop Enable, Frame Start control, Multiplex
Stop VP clock, Absent gain, Bias Enable, Tx Enable, Sync
P R E L I M I N A R Y
ADPCM Processor Status
READ DESCRIPTION
Remaining Sleep time
8-bit ADC data (RSSI)
Re Rate Buffer data
Bit Sync monitoring
Bit Sync monitoring
INT, WAKEUP pin control, 4-bit DAC data (PWLV)
SNR estimate
General-Purpose I/O port 0 direction control
General-Purpose I/O port 1 direction control
Start control
FCW value
ROMless Spread Spectrum Cordless Phone Controller
General-Purpose I/O port 0 data
General-Purpose I/O port 1 data
control, Sleep mode control
Clock Dividers, Use Core Bias,
SYLE polarity, search window
ADPCM Processor Command Table 33
ANT0/1 control, Sleep Period Table 26
Tx Rate Buffer data, control
RXSW, RFEON pin control
TXSW, RXSW pin control
WRITE DESCRIPTION
size, Bias Threshold
Rate Buffer address
MOD_PWR control
PAON pin control
Bit Sync control
Core Bias data
UW location
data
Z87001/Z87L01
TABLE #
Table 25
Table 27
Table 28
Table 29
Table 30
Table 31
Table 32
Table 36
Table 42
Table 44
Table 44
Table 44
Table 45
Table 46
Table 47
Table 47
Table 47
Table 47
Table 47
Table 47
Table 34
Table 35
Table 37
Table 43
Table 38
Table 39
Table 40
Table 41
Table 47
Table 49
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