Z87L0116ASC1937 Zilog, Z87L0116ASC1937 Datasheet - Page 46
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Z87L0116ASC1937
Manufacturer Part Number
Z87L0116ASC1937
Description
IC FHSS PHONE CTRL 144-VQFP
Manufacturer
Zilog
Datasheet
1.Z87L0116ASC.pdf
(51 pages)
Specifications of Z87L0116ASC1937
Controller Type
Phone Controller
Interface
Bus
Voltage - Supply
3 V ~ 3.6 V
Current - Supply
55mA
Operating Temperature
-20°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
144-QFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Z87001/Z87L01
ROMless Spread Spectrum Cordless Phone Controller
RESERVED
Field
RESERVED
CONTROL
Field
RESERVED
FS_INT_ENABLE
INTERRUPT_0_ENABLE ------9---------
INTERRUPT_2_ENABLE -------8--------
P0_WAKEUP_ENABLE
TX_PWR_DAC_DATA
Note:
P0_WAKEUP_ENABLE. When enabled, pins P0[3..0] are active low wake-up pins for the Z87001 sleep mode.
The input signal is internally debounced and synchronized to the bit clock. It is internally given a minimum duration of one bit to
RESERVED
Field
RESERVED
46
allow the software to exit sleep mode safely.
Bank 1
Bit Position
fedcba9876543210
Bank 1
Bit Position
fedcba9876543210
Bank 1
Bit Position
fedcb-----------
-----a----------
--------7654----
------------3210
Table 32. Bank 1 Register Description
Table 33. Bank 1 Register Description
Table 31. Bank 1 Register Description
P R E L I M I N A R Y
EXT7
R/W
EXT6
W
R/W
R/W
R/W
R/W
R/W
R/W
R
W
R
EXT5R/W Data
EXT3
EXT4
W
R
Data
0000*
Data
1xxx
x1xx
xx1x
xxx1
Xh
0*
0*
0*
1
1
1
0000h
Returns 0
No effect
Returns 0
No effect
Controls frame start interrupt (INT1)
Disables frame start interrupt
Enables frame start interrupt
Controls interrupt 0 (INT0 on P114)
Disables interrupt 0
Enables interrupt 0
Controls interrupt 2 (INT2 on P115)
Disables interrupt 2
Enables interrupt 2
Controls wake-up pins (P0[3..0])
Disables all wake-up pins
Enables P03 as wake-up pin (if in input mode)
Enables P02 as wake-up pin (if in input mode)
Enables P01 as wake-up pin (if in input mode)
Enables P00 as wake-up pin (if in input mode)
Access to Tx power 4-bit DAC output data
Sets output value
Returns 0
Must be left alone or written to 0000h (or
unpredictable results may occur)
Description
Description
Description
DS96WRL0800
Zilog