Z87L0116ASC1937 Zilog, Z87L0116ASC1937 Datasheet - Page 34

• Manufacturer Part Number: Z87L0116ASC1937
• Description: IC FHSS PHONE CTRL 144-VQFP
• Manufacturer: Zilog

Specifications of Z87L0116ASC1937

• Controller Type: Phone Controller
• Interface: Bus
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 55mA
• Operating Temperature: -20°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 144-QFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

REGISTER DESCRIPTION (Continued)
Z87001/Z87L01
ROMless Spread Spectrum Cordless Phone Controller
The bank is selectable in software by writing to the core’s
status register (see Table 24). Once a bank is selected,
Bank 0
Bank 1
Bank 2
Bank 3
Bank 3 Registers
Config 1
Field
RESERVED
VP_CLOCK
USE_CORE_BIAS --d-------------
SYLE_POLARITY ---c------------
WINDOW_SIZE
BIAS_THRESHOL
D
Notes:
34
1. VP_CLOCK. Internally synchronized to avoid glitches. Changes to this bit take effect immediately.
2. SYLE_POLARITY. Changes to this bit take effect immediately.
3. BIAS_THRESHOLD. The bias threshold must be coded as a negative value
(opposite of the threshold value) coded in 2’s complement. The nominal value for the
threshold is -46 (=D3h). Internally, this value is sign-extended to 13 bits.
Bank
Bank 3
Bit Position
f---------------
-e--------------
----ba98--------
-------76543210
xxxx xxxx x00x xxxx b
xxxx xxxx x01x xxxx b
xxxx xxxx x10x xxxx b
xxxx xxxx x11x xxxx b
Status Register
EXT0
R/W
Table 12. Bank 3 Registers
Table 11. Bank Switching
W
W
W
W
W
R
R
R
R
R
P R E L I M I N A R Y
Test point access, TDD switching control
Rate buffer access, miscellaneous
ADPCM processor interface, RF interface, etc.
Configuration, status, general-purpose port data and direction
0000
0001
•••
1111
XXh
Data Description
0*
0
1
1
0
1
Returns 0
Must be set to 1
Controls CLKOUT output pin (clock for ADPCM Processor).
Returns 0
CLOCKOUT=16.384 MHz
CLOCKOUT = 8.192
Controls which bias value is used by the downconverter’s
NCO as part of the automatic frequency control loop (AFC)
Returns 0
Uses BIAS_ERROR_DATA value from AFC hardware
Uses CORE_BIAS_DATA value from DSP core
Controls the polarity of the SYLE output pin (hop pulse)
Returns 0
SYLE is a positive pulse
SYLE is a negative pulse
Defines the search window size (in bits) for windowed search
mode (for Unique Word or SYNC_D words).
Returns 0
Window size=1
Window size =3 (1 1)
Window size = 31 (1 15)
Bias estimator threshold value
Returns 0
Sets the bias value
each of the eight external registers (EXT0 through EXT7)
can be accessed by a single-cycle software instruction.
Bank Function
DS96WRL0800
Zilog