IDT82V2108PX8 IDT, Integrated Device Technology Inc, IDT82V2108PX8 Datasheet - Page 132

• Manufacturer Part Number: IDT82V2108PX8
• Description: IC FRAMER T1/J1/E1 8CH 128-PQFP
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT82V2108PX8

• Controller Type: T1/E1/J1 Framer
• Interface: Parallel
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 160mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 128-MQFP, 128-PQFP
• Screening Level: Industrial
• Mounting: Surface Mount
• Operating Temperature (min): -40C
• Operating Temperature (max): 85C
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: 82V2108PX8

IDT82V2108
Table 59: Initialization of RPLC (Continued)
(b4, T1/J1-061H) is logic 1 and the BEI (b2, T1/J1-061H) is logic 0, the
pattern detector is in synchronization state.
then the configuration is shown in Table 60.
- Example For Testing T1/J1 System Backplane Integrity
T1/J1-00FH) should be set to logic 1 and the other registers are set as
above. Then the PRGD can be used to test the system backplane integ-
rity.
Operation
Table 60: Error Insertion
Then set the TEST in RPLC Payload Control register for CH2, CH4 and CH5.
The process is:
Then write 00H into the 06CH register to update the error counter registers.
Then read the registers from 06CH to 06FH to check the error numbers.
After the above setting, read the 061H register twice. If the SYNCV
Then insert errors into this link. Here suppose to insert 3 errors,
To test the T1/J1 system backplane integrity, the RXPATGEN (b2,
Register
0D3H
0D2H
0D3H
0D2H
0D3H
0D2H
Register
Register
0D3H
0D2H
0D3H
0D2H
0D3H
0D2H
0D3H
0D2H
064H
064H
064H
064H
064H
064H
Value
08H
02H
08H
04H
08H
05H
Set the TEST in RPLC Payload Con-
trol register for CH2.
Set the TEST in RPLC Payload Con-
trol register for CH4
Set the TEST in RPLC Payload Con-
trol register for CH5
Description
Value
Value
08H
00H
08H
00H
08H
00H
00H
15H
00H
16H
00H
17H
00H
18H
122
4.2.4.4
CAS/RBS Buffer, the indirect registers of these blocks must be initialized
to eliminate erroneous control data. The PCCE (b0, T1/J1-050H & b0,
T1/J1-030H & b0, T1/J1-040H) of these blocks must be set to logic 1 to
enable these blocks.
041H) must be checked before a new access request to the RPLC,
TPLC and RCRB indirect registers. When the BUSY is logic 0, the new
reading and writing access operations can be performed.
RCRB indirect registers. Figure 84 shows the reading sequence of the
RPLC, TPLC and RCRB indirect registers.
Figure 83. Writing Sequence of Indirect Register in T1/
Before using the Receive/Transmit Payload Control and Receive
Then the BUSY (b7, T1/J1-051H & b7, T1/J1-031H & b7, T1/J1-
Figure 83 shows the writing sequence of the RPLC, TPLC and
Using Payload Control and Receive CAS/RBS Buffer
RWB=0 and address is specified
in the Channel Indirect Address/
Y
Indirect Data Buffer Register
Data are set in the Channel
Control Register.
J1 Mode
Set PCCE=1
to be written
More data
BUSY=0
End
T1 / E1 / J1 OCTAL FRAMER
Y
N
N
March 5, 2009