TMC2072-MT SMSC, TMC2072-MT Datasheet - Page 84

• Manufacturer Part Number: TMC2072-MT
• Description: IC CTRLR CIRC 100-TQFP DUAL MODE
• Manufacturer: SMSC
• Series: CircLink™r

Specifications of TMC2072-MT

• Controller Type: I/O Controller
• Interface: Transceiver
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 40mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-TQFP, 100-VQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 638-1023

Peripheral Mode CircLink™ Controller
Datasheet
1: Sets via register , 0: Sets via external input pin.
TXEN (bit 8)
Setting this bit to 1 enables network participation. The initial value differs depending on the operation
mode; the starting status is 0 = offline in the Peripheral mode. This bit is the same as the TXEN bit in the
COMR6 register. If this bit is changed from 0 to 1, software reset is automatically executed (the software
reset is released automatically). Software reset is not applied when the bit is changed from 1 to 0.
1: Online state , 0: Offline state
ECRI (bit 7)
This bit stops automatic issuing of receive commands to the ARCNET core. The CircLink always receives;
to stop receiving, set this bit to 1. Moreover, this bit returns NAK to the free buffer enquiry (FBE) to the bit.
Returning this bit from 1 to 0 sets the receive flag registers RXF01 to RXF31 to the (initial) value of 1.
When CircLink receives a token issued by itself, ECRI is set. This causes a delay because setting/clearing
ECRI affects reception flags RXF0-RXF3. The delay is 52 ms; when the network data rate is 2.5 Mbps, and
scales accordingly for other rates.
1: Normal stop, 0: Normal operation
BRE (bit 6)
1: Receives broadcast packet , 0: No receive
TXM (bit 5)
1: Remote buffer sending mode , 0: Free-Format sending mode
RTO (bit 4)
This bit specifies the sending count in the Remote Buffer sending mode
1: One-packet sending , 0: Continuous auto-sending
WDMD (bit 3)
This bit specifies the data structure mode to access data register (COMR4) through an 8-bit bus. When
this bit is set to 1, to protect the higher and lower bytes of word data as one packet, it is necessary to
perform an access to COMR4 in the order of 08h to 09h (protection is unavailable in the order of 09h to
08h, 08h to 08h, and 09h to 09h). The rule is applicable for both write and read.
1: 16-bit data batch , 0: 8-bit data batch
nTKNRTY (bit 2)
Setting this bit to 1 disables token re-send. (original operation of ARCNET).
nACKNAK (bit 1)
Setting this bit to 1 generates reconfiguration in ACK/NAK deformation. (original operation of ARCNET).
nACLR (bit 0)
Setting this bit to 1 disables automatic clearance of receive flag in the readout of the last data in the free
format receive mode.
Revision 0.1 (06-07-07)
Page 84
SMSC TMC2072
DATASHEET