DS21Q42T Maxim Integrated Products, DS21Q42T Datasheet - Page 61

• Manufacturer Part Number: DS21Q42T
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

Table 15-1. HDLC/BOC CONTROLLER REGISTER LIST
HDLC Control Register (HCR)
HDLC Status Register (HSR)
HDLC Interrupt Mask Register (HIMR)
Receive HDLC Information Register (RHIR)
Receive BOC Register (RBOC)
Receive HDLC FIFO Register (RHFR)
Receive HDLC DS0 Control Register 1 (RDC1)
Receive HDLC DS0 Control Register 2 (RDC2)
Transmit HDLC Information Register (THIR)
Transmit BOC Register (TBOC)
Transmit HDLC FIFO Register (THFR)
Transmit HDLC DS0 Control Register 1 (TDC1)
Transmit HDLC DS0 Control Register 2 (TDC2)
15.1.2 Status Register for the HDLC
Four of the HDLC/BOC controller registers (HSR, RHIR, RBOC, and THIR) provide status information.
When a particular event has occurred (or is occurring), the appropriate bit in one of these four registers
will be set to a one. Some of the bits in these four HDLC status registers are latched and some are real
time bits that are not latched. Section 15.1.4 contains register descriptions that list which bits are latched
and which are not. With the latched bits, when an event occurs and a bit is set to a one, it will remain set
until the user reads that bit. The bit will be cleared when it is read and it will not be set again until the
event has occurred again. The real time bits report the current instantaneous conditions that are occurring
and the history of these bits is not latched.
Like the other status registers in the DS21Q42, the user will always proceed a read of any of the four
registers with a write. The byte written to the register will inform the DS21Q42 which of the latched bits
the user wishes to read and have cleared (the real time bits are not affected by writing to the status
register). The user will write a byte to one of these registers, with a one in the bit positions he or she
wishes to read and a zero in the bit positions he or she does not wish to obtain the latest information on.
When a one is written to a bit location, the read register will be updated with current value and it will be
cleared. When a zero is written to a bit position, the read register will not be updated and the previous
value will be held. A write to the status and information registers will be immediately followed by a read
of the same register. The read result should be logically AND’ed with the mask byte that was just written
and this value should be written back into the same register to insure that bit does indeed clear. This
second write step is necessary because the alarms and events in the status registers occur asynchronously
in respect to their access via the parallel port. This write–read–write (for polled driven access) or
write-read (for interrupt driven access) scheme allows an external microcontroller or microprocessor to
individually poll certain bits without disturbing the other bits in the register. This operation is key in
controlling the DS21Q42 with higher–order software languages.
NAME
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general control over the HDLC and BOC
allows/stops status bits to/from causing an interrupt
status information on transmit HDLC controller
enables/disables transmission of BOC codes
controllers
key status information for both transmit and receive
directions
status information on receive HDLC controller
status information on receive BOC controller
access to 64–byte HDLC FIFO in receive direction
controls the HDLC function when used on DS0
channels
access to 64–byte HDLC FIFO in transmit
direction
controls the HDLC function when used on DS0
channels
FUNCTION