DS21Q42T Maxim Integrated Products, DS21Q42T Datasheet - Page 67

• Manufacturer Part Number: DS21Q42T
• Description: IC FRAMER ENHANCED T1 4X 128TQFP
• Manufacturer: Maxim Integrated Products

Specifications of DS21Q42T

• Controller Type: T1 Framer
• Interface: Parallel/Serial
• Voltage - Supply: 2.97 V ~ 3.63 V
• Current - Supply: 75mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 128-TQFP, 128-VQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant

RHFR: RECEIVE HDLC FIFO (Address = 05 Hex)
THIR: TRANSMIT HDLC INFORMATION (Address = 06 Hex)
(MSB)
–
Note: The UDR bit is latched and will be cleared when read.
HDLC7
(MSB)
SYMBOL
SYMBOL
TEMPTY
HDLC7
HDLC6
HDLC5
HDLC4
HDLC3
HDLC2
HDLC1
HDLC0
TFULL
UDR
–
–
–
–
–
–
HDLC6
POSITION
POSITION
RHFR.7
RHFR.6
RHFR.5
RHFR.4
RHFR.3
RHFR.2
RHFR.1
RHFR.0
THIR.7
THIR.6
THIR.5
THIR.4
THIR.3
THIR.2
THIR.1
THIR.0
–
HDLC5
–
NAME AND DESCRIPTION
HDLC Data Bit 7. MSB of a HDLC packet data byte.
HDLC Data Bit 6.
HDLC Data Bit 5.
HDLC Data Bit 4.
HDLC Data Bit 3.
HDLC Data Bit 2.
HDLC Data Bit 1.
HDLC Data Bit 0. LSB of a HDLC packet data byte.
NAME AND DESCRIPTION
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Not Assigned. Could be any value when read.
Transmit FIFO Empty. A real–time bit that is set high when
the FIFO is empty.
Transmit FIFO Full. A real–time bit that is set high when the
FIFO is full.
Underrun. Set when the transmit FIFO unwantedly empties out
and an abort is automatically sent.
HDLC4
67 of 116
–
HDLC3
TEMPTY
HDLC2
TFULL
HDLC1
(LSB)
UDR
HDLC0
(LSB)