ISP1160BD01TM ST-Ericsson Inc, ISP1160BD01TM Datasheet - Page 12

• Manufacturer Part Number: ISP1160BD01TM
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1160BD01TM

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 568-1878-2; ISP1160BD/01,118; ISP1160BD01-T

Philips Semiconductors
9397 750 13963
Product data
8.4 FIFO buffer RAM access by PIO mode
Most of the ISP1160’s internal control registers are 16-bit wide. Some of the internal
control registers, however, are 32-bit wide.
internal control register is accessed. The complete cycle of accessing a 32-bit
register consists of a command phase followed by two data phases. In the two data
phases, the microprocessor first reads or writes the lower 16-bit data, followed by the
upper 16-bit data.
To further describe the complete access cycles of the internal control registers, the
status of some pins of the microprocessor bus interface are shown in
Since the ISP1160’s internal memory is structured as a FIFO buffer RAM, the FIFO
buffer RAM is mapped to dedicated register fields. Therefore, accessing the internal
FIFO buffer RAM is similar to accessing the internal control registers in multiple data
phases.
Fig 6. 16-bit register access cycle.
Fig 7. 32-bit register access cycle.
Fig 8. Accessing HC control registers.
data bus
Signals
CS_N
A0
RD_N,
WR_N
Rev. 05 — 24 December 2004
write command
Command code
Valid status
(16 bits)
RD_N = 1,
WR_N = 0
1
0
write command
(16 bits)
16-bit register access cycle
32-bit register access cycle
read/write data
(lower 16 bits)
RD_N = 0 (read) or
WR_N = 0 (write)
Register data
Valid status
(lower word)
Figure 7
0
0
read/write data
(16 bits)
Embedded USB Host Controller
shows how the ISP1160’s 32-bit
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
read/write data
(upper 16 bits)
MGT937
RD_N = 0 (read) or
WR_N = 0 (write)
t
Register data
(upper word)
Valid status
ISP1160
0
0
Figure
MGT938
t
004aaa370
8.
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