STW5093CYL ST-Ericsson Inc, STW5093CYL Datasheet
STW5093CYL
Specifications of STW5093CYL
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STW5093CYL Summary of contents
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FEATURES: Complete CODEC and FILTER system including: ■ 14 BIT LINEAR ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS. ■ 8 BIT COMPANDED ANALOG TO DIGITAL AND DIGITAL TO ANALOG CONVERTERS A- LAW OR µ-LAW. ■ TRANSMIT AND RECEIVE BAND-PASS ...
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STw5093 PIN CONNECTIONS (Top view) REMOUT BLOCK DIAGRAM MIC PREAMP 0/20dB MIC3- + MUTE MIC2- PG MIC1- MIC2+ MIC1+ MIC3+ VS & TE EARA OUTPUT 0 -> -30dB, 2dB STEP VFr 6dB OE VLr- -1 12dB VLr+ 1 EXTA OUTPUT ...
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PIN FUNCTION N° Pin 1 V Power supply input for the digital section REMOUT Remocon function digital output. 3 REMIN Remocon function input. An high level at this pin is detected as a non pressed key, while a ...
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STw5093 PIN FUNCTION (continued) N° Pin 24 VCCIO Power supply Input for the Digital I/O' Control data Output: Serial control/status information is shifted out from the STw5093 on this pin when CS- is low on the falling edges ...
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FUNCTIONAL DESCRIPTION 1.1 DEVICE OPERATION 1.1.1 Power on initialization: When power is first applied, power on reset circuitry initializes STw5093 and puts it into the power down state. Gain Control Registers for the various programmable gain amplifiers and programmable ...
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STw5093 mit rising edges of MCLK in delayed or non-delayed normal mode or on the falling edges of MCLK in non-de- layed reverse mode.A separate MBIAS output can be used to bias a microphone (bit register ...
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In the case of companded code only (bit register CR0) a time slot assignment circuit on chip may be used with all timing modes, allowing connection to one of the two B1 and B2 voice data ...
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STw5093 To read-back status information from STw5093, the first byte of the appropriate instruction is strobed in during the first CS- pulse, as defined in Table 1. CS- must be set low for a further 8 CCLK cycles, during which ...
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Table 1. Programmable Register Intructions Function Single byte Power up/down Write CR0 Read-back CR0 Write CR1 Read-back CR1 Write Data to receive path Read data from DR Write Data to DX Write CR4 Read-back CR4 Write CR5 Read-back CR5 Write ...
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STw5093 Table 2. Control Register CR0 Functions state at power on ...
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Table 4. Control Register CR2 Functions msb (1) Significant in companded mode only. Table 5. Control Registers CR3 Functions msb ...
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STw5093 Table 7. Control Register CR5 Functions Transmit amplifier Sidetone amplifier state at power ...
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Table 10. Control Register CR8 Functions f17 f16 f15 f14 f13 msb Table 11. Control Register CR9 Functions f27 f26 f25 f24 f23 msb Table 12. Control Register CR10 Functions ...
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STw5093 CONTROL REGISTER CR0 First byte of a READ or a WRITE instruction to Control Register CR0 is as shown in TABLE 1. Second byte is as shown in TABLE 2. Master Clock / Auxiliary Clock Frequency Selection A master ...
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Latch output control Bit DO controls directly logical status of latch output LO: ie, a "ZERO" written in bit DO puts the output LO at logical 1, while a "ONE" written in bit DO sets the output LO to zero. ...
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STw5093 Transmit Input Selection MIC1 or MIC2 or MIC3 or transmit mute can be selected with bits 6 and 7 (VS and TE). Transmit gain can be adjusted within a 22.5 dB range in 1.5 dB step with Register CR5. ...
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Earpiece amplifier gain selection: Earpiece Receive gain can be programmed step from -30 dB relative to the maximum with bits dBmO voltage at the output of the amplifier on pin ...
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STw5093 and where CR8 and CR9 are decimal equivalents of the binary values of the CR8 and CR9 registers respectively. Thus, any frequency between 7.8 Hz and 1992 Hz may be selected in 7.8 Hz step. If "halved frequency tone ...
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CONTROL REG- ISTER CR8 and CR9. CONTROL REGISTER CR11 Bit BE(7) permits connection squarewave PWM Ring signal, amplitude modulated or not ...
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STw5093 TIMING DIAGRAM Figure 2. Non Delayed Data Timing Mode (Normal) (*) Figure 3. Delayed Data Timing Mode (*) (*) In the case of companded code the timing is applied to 8 bits instead of 16 bits. 20/34 ...
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TIMING DIAGRAM Figure 4. Non Delayed Reverse Data Timing Mode (* tHMFR 1 2 MCLK tSFMR tHMFR FS tDFD tDMDR (*) In the case of companded code the timing is applied to 8 bits instead of ...
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STw5093 ABSOLUTE MAXIMUM RATINGS V to GND CC ≤ 3.3V) Voltage at MIC (V CC Current at V and Current at any digital output Voltage at any digital input (V CCIO Storage temperature range Lead Temperature (wave ...
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TIMING SPECIFICATIONS (continued) PCM INTERFACE TIMING (continued) Symbol Parameter t Delay Time, MCLK low to DX DMZ disabled t Delay Time, FS high to data valid DFD t Setup Time, DR valid to MCLK SDM receive edge t Hold Time, ...
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STw5093 TIMING SPECIFICATIONS (continued) SERIAL CONTROL PORT TIMING (continued) Symbol Parameter t Delay Time CS-high or 8th CCLK DDZ low to CO high impedance whichever comes first t Hold Time, 8th CCLK high to CS- HSC high t Set up ...
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Figure 6. A.C. TESTING INPUT, OUTPUT WAVEFORM INTPUT/OUTPUT 0.8V CCIO 0.2V CCIO AC Testing: inputs are driven at 0.8V Timing measurements are made at 0.7V ANALOG INTERFACES Symbol Parameter R Switch Resistance for MBIAS Microphone bias I Input Leakage MIC ...
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STw5093 TRANSMISSION CHARACTERISTICS (unless otherwise specified, V typical characteristics are specified 1015.625 Hz; all signal are referenced to GND) AMPLITUDE RESPONSE (Maximum, Nominal, and Minimum Levels) Transmit path - Absolute levels at MIC1 / MIC2 / ...
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AMPLITUDE RESPONSE(continued) Transmit path (continued) Symbol Parameter G Transmit Gain Variation with XAF frequency G Transmit Gain Variation with XAL signal level (*) The limit at frequencies between 4600Hz and 8000Hz lies on a straight line connecting the two frequencies ...
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STw5093 AMPLITUDE RESPONSE(continued) Receive path (continued) Symbol Parameter G Receive Gain Variation with RAV Supply G Receive Gain Variation with RAF frequency (V and HPB = 0 Receive Gain Variation with frequency (V and ...
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ENVELOPE DELAY DISTORTION WITH FREQUENCY Symbol Parameter DXA Tx Delay, Absolute DXR Tx Delay, Relative DRA Rx Delay, Absolute DRR Rx Delay, Relative NOISE Symbol Parameter NXP Tx Noise, P weighted (up to 35dB) NRP Rx Noise, linear weighted (*) ...
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STw5093 DISTORTION Symbol Parameter S (*) Signal to Total Distortion TDX (up to 35dB gain) Typical values are measured with 30.5dB gain S Single Frequency Distortion transmit DFx S (*) Signal to Total Distortion (V TDRE ( up to 20dB ...
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AUDIO CODEC APPLICATIONS Figure 7. Application Note for Microphone Connections. SINGLE ENDED MODE 1KΩ 2KΩ 4KΩ 0.47µF 22µF 4KΩ 0.47µF Figure 8. Application Note for V CERAMIC RECEIVERS (50nF Lr+ STw5093 EP V Lr- R D98TL397A R must ...
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STw5093 POWER SUPPLY NOTES Two different strategies can be used to minimize power supply noise/interference. a) Recommended strategy: keep analog and digital power supply rails separate. This requires to use two sets of capacitors, one from AVCC to AGND and ...
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DIM. MIN. TYP. MAX. MIN. A 1.10 A1 0.05 0.15 0.002 A2 0.85 0.90 0.95 0.033 b 0.17 0.27 0.007 c 0.09 0.20 0.004 D 7.70 7.80 7.90 0.303 E 6.40 e 0.50 E1 4.30 4.40 4.50 0.169 L ...
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STW5093 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its ...