ISP1362BDFA ST-Ericsson Inc, ISP1362BDFA Datasheet

IC USB OTG CONTROLLER 64-LQFP

ISP1362BDFA

Manufacturer Part Number
ISP1362BDFA
Description
IC USB OTG CONTROLLER 64-LQFP
Manufacturer
ST-Ericsson Inc
Datasheet

Specifications of ISP1362BDFA

Controller Type
USB 2.0 Controller
Interface
Parallel/Serial
Voltage - Supply
3 V ~ 3.6 V
Operating Temperature
-40°C ~ 85°C
Mounting Type
Surface Mount
Package / Case
64-LQFP
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Current - Supply
-
Other names
568-1219
ISP1362BD,151
ISP1362BD-S

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Dear customer,
As from August 2
ST-NXP Wireless.
As a result, the following changes are applicable to the attached document.
If you have any questions related to the document, please contact our nearest sales office.
Thank you for your cooperation and understanding.
ST-NXP Wireless
Company name - NXP B.V. is replaced with ST-NXP Wireless.
Copyright - the copyright notice at the bottom of each page “© NXP B.V. 200x. All
rights reserved”, shall now read: “© ST-NXP Wireless 200x - All rights reserved”.
Web site -
Contact information - the list of sales offices previously obtained by sending
an email to
under Contacts.
http://www.nxp.com
salesaddresses@nxp.com
nd
2008, the wireless operations of NXP have moved to a new company,
IMPORTANT NOTICE
is replaced with
, is now found at
http://www.stnwireless.com
http://www.stnwireless.com
www.stnwireless.com

Related parts for ISP1362BDFA

ISP1362BDFA Summary of contents

Page 1

IMPORTANT NOTICE Dear customer from August 2 2008, the wireless operations of NXP have moved to a new company, ST-NXP Wireless result, the following changes are applicable to the attached document. ● Company name - NXP ...

Page 2

ISP1362 Single-chip Universal Serial Bus On-The-Go Controller Rev. 05 — 8 May 2007 1. General description The ISP1362 is a single-chip Universal Serial Bus (USB) On-The-Go (OTG) controller integrated with the advanced NXP Slave Host Controller and the NXP ISP1181B ...

Page 3

NXP Semiconductors N Supports integrated physical 4096 bytes of multiconfiguration memory N Supports all four types of USB transfers: control, bulk, interrupt and isochronous N Supports multiframe buffering for isochronous transfer N Supports automatic interrupt polling rate mechanism N Supports ...

Page 4

NXP Semiconductors 3.1 Host/peripheral roles I Mobile phone to/from: N Mobile phone: exchange contact information N Digital still camera: e-mail pictures or upload pictures to the web N MP3 player: upload, download and broadcast music N Mass storage: upload and ...

Page 5

NXP Semiconductors 4. Ordering information Table 1. Ordering information Type number Package Name ISP1362BD LQFP64 ISP1362EE TFBGA64 ISP1362_5 Product data sheet Description plastic low profile quad flat package; 64 leads; body 10 plastic thin fine-pitch ball grid array package; 64 ...

Page 6

POWER-ON RESET RESET H_SUSPEND/ 33 H_WAKEUP 13 18, 63 D[15: BUS A0 62 INTERFACE A1 28 DACK1 29 DACK2 24 DREQ1 ...

Page 7

NXP Semiconductors 6. Pinning information 6.1 Pinning DGND DGND D10 13 D11 D12 15 16 ...

Page 8

NXP Semiconductors 6.2 Pin description Table 2. Pin description [1] Symbol Pin LQFP64 TFBGA64 DGND DGND ...

Page 9

NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin LQFP64 TFBGA64 D12 15 J1 D13 16 K1 D14 17 K2 D15 18 J3 DGND ...

Page 10

NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin LQFP64 TFBGA64 DREQ2 DGND 27 K7 DACK1 28 J8 DACK2 29 K8 INT1 30 J9 INT2 31 K9 RESET 32 K10 H_SUSPEND/ 33 J10 ...

Page 11

NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin LQFP64 TFBGA64 H_PSW1 35 H10 H_PSW2 36 G9 DGND 37 G10 CLKOUT F10 H_OC2 41 E10 H_OC1 D10 ...

Page 12

NXP Semiconductors Table 2. Pin description …continued [1] Symbol Pin LQFP64 TFBGA64 OTG_DM1 49 A9 OTG_DP1 50 B8 AGND CP_CAP1 53 A7 CP_CAP2 BUS DD(5V) DGND ...

Page 13

NXP Semiconductors 7. Functional description 7.1 On-The-Go (OTG) controller The OTG Controller provides all the control, monitoring and switching functions required in OTG operations. 7.2 Advanced NXP Slave Host Controller The advanced NXP Slave Host Controller is designed for highly ...

Page 14

NXP Semiconductors 7.9 GoodLink Indication of a good USB connection is provided through the GoodLink technology (open-drain, maximum current: 4 mA). During enumeration, LED indicators momentarily blink on corresponding to the enumeration traffic of the ISP1362 ports. The LED also ...

Page 15

NXP Semiconductors 8.1 Memory organization The buffer memory in the Host Controller uses a multiconfigurable direct addressing architecture. The 4096 bytes Host Controller buffer memory is shared by the ISTL0, ISTL1, INTL and ATL buffers. ISTL0 and ISTL1 are used ...

Page 16

NXP Semiconductors Fig 4. Recommended values of the ISP1362 buffer memory allocation The INTL and ATL buffers use ‘blocked memory management’ scheme to enhance the status and control capability of each and every individual Philips Transfer Descriptor (PTD) structure. The ...

Page 17

NXP Semiconductors Fig 5. A sample snapshot of the ATL or INTL memory management scheme Figure 5 block size of 64 bytes. The HCD may put a PTD with payload size bytes but not more. Depending ...

Page 18

NXP Semiconductors Fig 6. A sample snapshot of the ISTL memory management scheme 8.1.2 Memory organization for the Peripheral Controller The ISP1362 Peripheral Controller has a total of 2462 bytes of built-in buffer memory. This buffer memory is multiconfigurable to ...

Page 19

NXP Semiconductors Fig 7. Peripheral Controller buffer memory organization The buffer memory is configured by DcEndpointConfiguration Registers (ECRs). Although the control endpoint has a fixed configuration, all 16 endpoints (control OUT, control IN and 14 programmable endpoints) must be configured ...

Page 20

NXP Semiconductors Fig 8. PIO interface between a microprocessor and the ISP1362 8.3 DMA mode The ISP1362 also provides DMA mode for external microprocessors to access the internal buffer memory of the ISP1362. The DMA operation enables data to be ...

Page 21

NXP Semiconductors 8.4 PIO access to internal control registers Table 5 decoding must combine with the chip select signal (CS) and address lines (A1 and A0). The direction of access of I/O ports, however, is controlled by the RD and ...

Page 22

NXP Semiconductors Fig 11. Access to internal control registers A0/ D[15:0] Fig 12. PIO register access ISP1362_5 Product data sheet CMD/DATA SWITCH host or device 1 command port bus interface 0 data port A0 When ...

Page 23

NXP Semiconductors A0/ D[15:0] Command phase A0/ D[15:0] Command phase Fig 13. PIO access for a 16-bit or 32-bit register The following is a sample code for PIO access to internal control registers: unsigned ...

Page 24

NXP Semiconductors result = result_h; result = result<<16; result = result+result_l; return(result); } void write_reg32(unsigned char reg_no, unsigned long data2write) { unsigned int low_word; unsigned int hi_word; low_word=data2write&0x0000FFFF; hi_word=(data2write&0xFFFF0000)>>16; outport(hc_com,reg_no|0x80); // Command phase outport(hc_data,low_word); // Data phase outport(hc_data,hi_word); // Data ...

Page 25

NXP Semiconductors void Set_DirAddrLen(unsigned int data_length,unsigned int addr) { unsigned long RegData = 0; RegData =(long)(addr&0x7FFF); RegData|=(((long)data_length)<<16); write_reg32(HcDirAddrLen,RegData); } After the proper value is written to the HcDirectAddressLength register, data is accessible from the HcDirectAddressData register (called as HcDirAddr_Port in ...

Page 26

NXP Semiconductors cnt= outport(hc_data,*(a_ptr+cnt)); // hc_data is system address of HC cnt++; } while(cnt<(word_size)); Remark: The HcTransferCounter register counts the number of bytes even though the transfer is in number of words. Therefore, the transfer counter must be ...

Page 27

NXP Semiconductors • HcTransferCounter – If DMACounterEnable of the HcDMAConfiguration register is set (that is, the DMA counter is enabled), HcTransferCounter must be set to the number of bytes to be transferred. • HcDMAConfiguration – Read or write DMA (bit ...

Page 28

NXP Semiconductors OtgInterruptEnable register OTG_TMR_IE B_SE0_SRP_IE A_SRP_DET_IE OTG_RESUME_IE OTG_SUSPND_IE RMT_CONN_IE B_SESS_VLD_IE A_SESS_VLD_IE B_SESS_END_IE A_VBUS_VLD_IE ID_REG_IE OtgInterrupt register OTG_TMR_TIMEOUT B_SE0_SRP A_SRP_DET OTG_RESUME OTG_SUSPND RMT_CONN_C B_SESS_VLD_C A_SESS_VLD_C B_SESS_END_C A_VBUS_VLD_C ID_REG_C HcInterruptEnable register MIE RHSC FNO HcInterruptStatus register RHSC ...

Page 29

NXP Semiconductors Interrupt level 2 (OPR group) contains six possible interrupt events (recorded in the HcInterruptStatus register). When any of these events occurs, the corresponding bit will be set to logic 1, and if the corresponding bit in the HcInterruptEnable ...

Page 30

NXP Semiconductors The DcMode register (bit 3) is the overall Peripheral Controller interrupt enable. DcHardwareConfiguration determines the following features: • Level-triggered or edge-triggered (bit 1) • Output polarity (bit 0) For details on the interrupt logic in the Peripheral Controller, ...

Page 31

NXP Semiconductors 9. Power-On Reset (POR) When V will typically be 800 ns. The pulse is started when V To give a better view of the functionality, dips and t4 to t5. If the dip at ...

Page 32

NXP Semiconductors 10. On-The-Go (OTG) Controller 10.1 Introduction OTG is a supplement to the Hi-Speed USB (USB 2.0) specification that augments existing USB peripherals by adding to these peripherals limited host capability to support other targeted USB peripherals ...

Page 33

NXP Semiconductors If the B-device wants to start a session, it must initiate SRP by ‘data line pulsing’ and ‘V pulsing’. When the A-device detects any of these SRP events, it turns on its V BUS (note that only the ...

Page 34

NXP Semiconductors – Set A_SRP_DET_EN (bit 10) of the OtgControl register to logic 1. • Steps to enable the SRP detection by data line pulsing: – Set A_SEL_SRP (bit 9) of the OtgControl register to logic 1. – Set A_SRP_DET_EN ...

Page 35

NXP Semiconductors HNP request from the B-device. At this point, the B-device becomes a host and asserts bus reset to start using the bus. The B-device must assert the bus reset (that is, SE0) within the time ...

Page 36

NXP Semiconductors START id | a_bus_req | (a_sess_vld/ & b_conn/) a_wait_vfall drv_vbus/ loc_conn/ loc_sof a_bus_drop a_peripheral drv_vbus loc_conn loc_sof/ b_conn/ & a_set_b_hnp_en id | a_bus_drop | a_aidl_bdis_tmout a_suspend drv_vbus loc_conn/ loc_sof/ Fig 18. Dual-role A-device state diagram ISP1362_5 ...

Page 37

NXP Semiconductors Fig 19. Dual-role B-device state diagram 10.4.3 HNP implementation and OTG state machine The OTG state machine is the software behind all the OTG functionality implemented in the microprocessor system that is connected to the ISP1362. ...

Page 38

NXP Semiconductors 1. Set the polarity and level-triggering or edge-triggering mode of the HcHardwareConfiguration register (bits 1 and 2, default is level-triggered, active LOW). 2. Set the corresponding bits of the OtgInterruptEnable register (bits some of ...

Page 39

NXP Semiconductors Table 7. Capacitance The connection of the external capacitor (C Figure 20. Remark: If the internal charge pump is not used, C Fig 20. External capacitors connection 11. USB Host Controller (HC) 11.1 USB ...

Page 40

NXP Semiconductors USBOperational write USBSuspend write Fig 21. USB Host Controller states of the ISP1362 The USB states are reflected in the HostControllerFunctionalState (HCFS) field of the HcControl register. The HCD is allowed to perform only USB state transitions shown ...

Page 41

NXP Semiconductors 9. Read the HcRhPortStatus[1] and HcRhPortStatus[2] registers. The hexadecimal value of one of the registers must change to 0001 0101h, indicating that a device connection has been detected. 10. Write 32-bit hexadecimal value 0000 0102h into either HcRhPortStatus[1] ...

Page 42

NXP Semiconductors structure in the memory buffer will have an offset of 0 bytes and the second PTD structure will have an offset of 40 bytes [sum of the block size (32 bytes) and the PTD header size (8 bytes)]. ...

Page 43

NXP Semiconductors Table 9. Generic PTD structure: bit allocation [1] Bit 7 Byte 0 Byte 1 CompletionCode[3:0] Byte 2 Byte 3 EndpointNumber[3:0] Byte 4 Byte 5 B5[7] B5[6] Byte 6 reserved Byte 7 [1] All reserved bits should be set ...

Page 44

NXP Semiconductors Table 11. Generic PTD structure: bit description Name Status update by HC ActualBytes[9:0] Yes CompletionCode[3:0] Yes Active Yes Toggle Yes MaxPktSize[9:0] No EndpointNumber[3:0] No ISP1362_5 Product data sheet Description This field contains the number of bytes that were ...

Page 45

NXP Semiconductors Table 11. Generic PTD structure: bit description Name Status update by HC B3[3] Last (PTD) No Speed (low) No TotalBytes[9:0] No B5[6] Ping-Pong No B5[7] Paired No DirToken[1:0] No FunctionAddress[6:0] No B7[7:5] PollingRate No B7[4:0] StartingFrame (interrupt only) ...

Page 46

NXP Semiconductors 11.5.1 Sending a USB device request (Get Descriptor) This section provides an example on how a USB transfer descriptor ‘Get Descriptor’ (commonly used in device enumeration) is used to illustrate the ISP1362 PTD application. To perform this example, ...

Page 47

NXP Semiconductors 11.6 Features of the interrupt transfer • An interrupt transaction is periodically sent out, according to the ‘interrupt polling rate’ as defined in the PTD. • An interrupt transaction causes an interrupt to the CPU only if the ...

Page 48

NXP Semiconductors In general applications, you can use a P-channel MOSFET as the power switch for V Connect the 5 V power supply to the source pole of the P-channel MOSFET, V drain pole, and H_PSWn to the gate pole. ...

Page 49

NXP Semiconductors Fig 24. Using external overcurrent detection circuit 11.8.3 Overcurrent detection circuit using internal charge pump in OTG mode When port 1 is operating in OTG mode, you may choose to use the internal charge pump to provide 5 ...

Page 50

NXP Semiconductors 11.8.4 Overcurrent detection circuit using external 5 V power source in OTG mode In OTG mode using external 5 V power source for V the same as that for non-OTG mode (see 11.9 ISP1362 Host Controller power management ...

Page 51

NXP Semiconductors 12.1 Peripheral Controller data transfer operation The following sessions explain how the Peripheral Controller in the ISP1362 handles an IN data transfer and an OUT data transfer data transfer means transfer from the ISP1362 to an ...

Page 52

NXP Semiconductors 12.2 Device DMA transfer 12.2.1 DMA for an IN endpoint (internal Peripheral Controller to the external USB host) When the internal DMA handler is enabled and at least one buffer (ping or pong) is free, the DREQ2 line ...

Page 53

NXP Semiconductors 12.3 Endpoint description 12.3.1 Endpoints with programmable buffer memory size Each USB device is logically composed of several independent endpoints. An endpoint acts as a terminus of a communication flow between the USB host and the USB device. ...

Page 54

NXP Semiconductors Table 15. FFOSZ[3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Each programmable buffer memory can independently be configured by using its ECR, but the total physical size of all ...

Page 55

NXP Semiconductors When reset by hardware or by the USB bus occurs, the Peripheral Controller disables all endpoints and clears all ECRs, except the control endpoint that is fixed and always enabled. An endpoint initialization can be done at any ...

Page 56

NXP Semiconductors 12.4.1 Selecting an endpoint for the DMA transfer The target endpoint for DMA access is selected using bits EPDIX[3:0] of the DcDMAConfiguration register, as shown in is automatically set by the EPDIR bit in the associated ECR, to ...

Page 57

NXP Semiconductors The 8237 has two control signals for each DMA channel: DREQ (DMA Request) and DACK (DMA Acknowledge). General control signals are HRQ (Hold Request) and HLDA (Hold Acknowledge). The bus operation is controlled by MEMR (Memory Read), MEMW ...

Page 58

NXP Semiconductors 12. The CPU acknowledges control of the bus by de-asserting HLDA. After activating the bus control lines (MEMR, MEMW, IOR and IOW) and address lines, the CPU resumes the execution of instructions. For a typical bulk transfer, the ...

Page 59

NXP Semiconductors 12.4.3.2 Isochronous endpoints A DMA transfer to or from an isochronous endpoint can be terminated by any of the following conditions (bit names refer to the DcDMAConfiguration register, see and Table • The DMA transfer completes as programmed ...

Page 60

NXP Semiconductors The Peripheral Controller in the ISP1362 will remain in the suspend state for at least 5 ms, before responding to external wake-up events, such as global resume, bus traffic, CS active or LOW pulse on the D_SUSPEND/D_WAKEUP pin. ...

Page 61

NXP Semiconductors 1. The internal oscillator and the PLL multiplier are re-enabled. When stabilized, clock signals are routed to all internal circuits of the Peripheral Controller in the ISP1362. 2. The D_SUSPEND/D_WAKEUP pin goes LOW, and the RESUME bit of ...

Page 62

NXP Semiconductors Table 23. Bit ISP1362_5 Product data sheet OtgControl register: bit description Symbol Description reserved OTG_SE0_ This bit is used by the Host Controller to send ...

Page 63

NXP Semiconductors Table 23. Bit 13.2 OtgStatus register (R: 67h) Code (Hex): 67 — read only Table 24. OtgStatus register: bit allocation Bit 15 Symbol Reset - Access - Bit 7 Symbol reserved Reset - Access - ...

Page 64

NXP Semiconductors Table 25. Bit 13.3 OtgInterrupt register (R/W: 68h/E8h) Code (Hex): 68 — read Code (Hex): E8 — write Table 26. OtgInterrupt register: bit allocation Bit 15 Symbol Reset - Access - Bit 7 Symbol ...

Page 65

NXP Semiconductors Table 27. Bit ISP1362_5 Product data sheet OtgInterrupt register: bit description Symbol Description - reserved OTG_TMR_ This bit is set whenever the OTG timer attains time-out. Writing ...

Page 66

NXP Semiconductors Table 27. Bit 13.4 OtgInterruptEnable register (R/W: 69h/E9h) Code (Hex): 69 — read Code (Hex): E9 — write Table 28. OtgInterruptEnable register: bit allocation Bit 15 Symbol Reset - Access - Bit 7 Symbol OTG_ ...

Page 67

NXP Semiconductors Table 29. Bit 13.5 OtgTimer register (R/W: 6Ah/EAh) Code (Hex): 6A — read Code (Hex): EA — write Table 30. OtgTimer register: bit allocation Bit 31 Symbol START_ TMR Reset 0 ...

Page 68

NXP Semiconductors Table 31. Bit 13.6 OtgAltTimer register (R/W: 6Ch/ECh) Code (Hex): 6C — read Code (Hex): EC — write Table 32. OtgAltTimer register: bit allocation Bit 31 Symbol START_ TMR Reset 0 ...

Page 69

NXP Semiconductors Table 33. Bit 14. Host Controller registers The Host Controller contains a set of on-chip control registers. These registers can be read or written by the Host Controller Driver (HCD). The ...

Page 70

NXP Semiconductors Table 34. Host Controller registers overview Command (Hex) Register Read Write 12 92 HcRhDescriptorA 13 93 HcRhDescriptorB 14 94 HcRhStatus 15 95 HcRhPortStatus[ HcRhPortStatus[ HcHardwareConfiguration 21 A1 HcDMAConfiguration 22 A2 HcTransferCounter ...

Page 71

NXP Semiconductors 14.1 HC control and status registers 14.1.1 HcRevision register (R: 00h) The bit allocation of the HcRevision register is given in Code (Hex): 00 — read only Table 35. HcRevision register: bit allocation Bit 31 Symbol Reset - ...

Page 72

NXP Semiconductors Bit 23 Symbol Reset - Access - Bit 15 Symbol Reset - Access - Bit 7 Symbol HCFS[1:0] Reset 0 Access R/W R/W Table 38. Bit ...

Page 73

NXP Semiconductors 14.1.3 HcCommandStatus register (R/W: 02h/82h) The HcCommandStatus register bytes register, and the bit allocation is given in Table 39. This register is used by the Host Controller to receive commands issued by the HCD, and ...

Page 74

NXP Semiconductors Table 40. Bit 14.1.4 HcInterruptStatus register (R/W: 03h/83h) This register (bit allocation: hardware interrupts. When an event occurs, the Host Controller sets the corresponding bit in this register. ...

Page 75

NXP Semiconductors Table 42. Bit 14.1.5 HcInterruptEnable register (R/W: 04h/84h) Each enable bit in the HcInterruptEnable register corresponds to an associated interrupt bit in the HcInterruptStatus register. The HcInterruptEnable register ...

Page 76

NXP Semiconductors Bit 23 Symbol Reset - Access - Bit 15 Symbol Reset - Access - Bit 7 Symbol reserved RHSC Reset - Access - R/W Table 44. Bit ...

Page 77

NXP Semiconductors Table 45. HcInterruptDisable register: bit allocation Bit 31 Symbol MIE Reset 0 Access R/W Bit 23 Symbol Reset - Access - Bit 15 Symbol Reset - Access - Bit 7 Symbol reserved RHSC Reset - Access - R/W ...

Page 78

NXP Semiconductors adjustments on FrameInterval by writing a new value over the present one at each SOF. This provides the programmability necessary for the Host Controller to synchronize with an external clocking resource and to adjust any unknown local clock ...

Page 79

NXP Semiconductors Code (Hex): 8E — write Table 49. HcFmRemaining register: bit allocation Bit 31 Symbol FRT Reset 0 Access R/W Bit 23 Symbol Reset - Access - Bit 15 Symbol reserved Reset - Access - Bit 7 Symbol Reset ...

Page 80

NXP Semiconductors Table 51. HcFmNumber register: bit allocation Bit 31 Symbol Reset - Access - Bit 23 Symbol Reset - Access - Bit 15 Symbol Reset 0 Access R Bit 7 Symbol Reset 0 Access R Table 52. Bit 31 ...

Page 81

NXP Semiconductors Bit 15 Symbol Reset - Access - Bit 7 Symbol Reset 0 Access R/W R/W Table 54. Bit 14.3 HC root hub registers All registers included in this partition are dedicated to ...

Page 82

NXP Semiconductors Code (Hex): 92 — write Table 55. HcRhDescriptorA register: bit description Bit 31 Symbol Reset 1 Access R/W R/W Bit 23 Symbol Reset - Access - Bit 15 Symbol reserved Reset - Access - Bit 7 Symbol Reset ...

Page 83

NXP Semiconductors Table 56. Bit 14.3.2 HcRhDescriptorB register (R/W: 13h/93h) The HcRhDescriptorB register is the second of two registers describing the characteristics of the root hub. These fields are written during initialization to ...

Page 84

NXP Semiconductors Table 58. Bit 14.3.3 HcRhStatus register (R/W: 14h/94h) The HcRhStatus register is divided into two parts. The lower word of a double-word represents the hub status ...

Page 85

NXP Semiconductors Table 60. Bit 14.3.4 HcRhPortStatus[1:2] register (R/W [1]: 15h/95h; [2]: 16h/96h) The HcRhPortStatus[1:2] register is used to control and report port events on a per-port ...

Page 86

NXP Semiconductors Bit 23 Symbol reserved Reset - Access - Bit 15 Symbol Reset - Access - Bit 7 Symbol reserved Reset - Access - Table 62. Bit ISP1362_5 Product data sheet 22 ...

Page 87

NXP Semiconductors Table 62. Bit ISP1362_5 Product data sheet HcRhPortStatus[1:2] register: bit description Symbol Description CSC ConnectStatusChange: This bit is set whenever a connect or disconnect event occurs. The HCD writes ...

Page 88

NXP Semiconductors Table 62. Bit ISP1362_5 Product data sheet HcRhPortStatus[1:2] register: bit description Symbol Description PRS On read PortResetStatus: When this bit is set by a write to SetPortReset, port reset signaling is asserted. When reset is ...

Page 89

NXP Semiconductors Table 62. Bit 1 0 14.4 HC DMA and interrupt control registers 14.4.1 HcHardwareConfiguration register (R/W: 20h/A0h) The bit allocation of the HcHardwareConfiguration register is given in Code (Hex): 20 — read Code (Hex): A0 — write Table ...

Page 90

NXP Semiconductors Table 64. Bit ISP1362_5 Product data sheet HcHardwareConfiguration register: bit description Symbol Description DisableSuspend_Wakeup This bit when set to logic 1 disables the function of the D_SUSPEND/D_WAKEUP and ...

Page 91

NXP Semiconductors Table 64. Bit 14.4.2 HcDMAConfiguration register (R/W: 21h/A1h) Table 65 Code (Hex): 21 — read Code (Hex): A1 — write Table 65. HcDMAConfiguration register: bit allocation Bit 15 Symbol Reset - ...

Page 92

NXP Semiconductors Table 66. Bit Table 67. Bit 14.4.3 HcTransferCounter register (R/W: 22h/A2h) Regardless of PIO or DMA data transfer modes, this register is used to initialize the number ...

Page 93

NXP Semiconductors Table 69. Hc PInterrupt register: bit allocation Bit 15 Symbol Reset - Access - Bit 7 Symbol INTL_IRQ ClkReady Reset 0 Access R/W R/W Table 70. Bit ISP1362_5 ...

Page 94

NXP Semiconductors Table 70. Bit 14.4.5 Hc PInterruptEnable register (R/W: 25h/A5h) Bits this register are the same as those in the Hc PInterrupt register. The bits in this register are used together with ...

Page 95

NXP Semiconductors Table 72. Bit 14.5 HC miscellaneous registers 14.5.1 HcChipID register (R: 27h) This register contains the ID of the ISP1362. The upper byte identifies ...

Page 96

NXP Semiconductors Table 74. HcScratch register: bit description Bit Symbol Scratch[15:0] 14.5.3 HcSoftwareReset register (W: A9h) This register provides a means for the software reset of the Host Controller. To reset the Host Controller, the HCD must ...

Page 97

NXP Semiconductors Table 77. Bit 14.6.2 HcDirectAddressLength register (R/W: 32h/B2h) The HcDirectAddressLength register is used for direct addressing of the ISTL, INTL or ATL buffers. This register specifies the starting address ...

Page 98

NXP Semiconductors Bit 7 Symbol Reset 0 Access R/W R/W Table 79. Bit 14.6.3 HcDirectAddressData register (R/W: 45h/C5h) This is a data port for the HCD to access the ISTL, INTL or ATL ...

Page 99

NXP Semiconductors Table 82. HcISTL0BufferPort register: bit description Bit Symbol Access DataWord[15:0] R/W The HCD is first required to initialize the HcTransferCounter register with the byte count to be transferred and check the HcBufferStatus register. The HCD ...

Page 100

NXP Semiconductors Bit 7 Symbol Reset - Access - Table 85. Bit 14.8 Interrupt transfer registers 14.8.1 HcINTLBufferSize register (R/W: 33h/B3h) This register allows you to allocate the size of the INTL buffer to ...

Page 101

NXP Semiconductors 14.8.3 HcINTLBlkSize register (R/W: 53h/D3h) The ISP1362 requires the INTL buffer to be partitioned into several equal sized blocks so that the Host Controller can skip the current PTD and proceed to process the next PTD easily. The ...

Page 102

NXP Semiconductors PTD if the HCD has reset its corresponding skipped bit to logic 0. Clearing the corresponding bit in the HcINTLPTDSkipMap register when there is no valid data in the block will cause unpredictable behavior of the Host Controller. ...

Page 103

NXP Semiconductors Table 94. Bit 14.9 Control and bulk transfer (aperiodic transfer) registers 14.9.1 HcATLBufferSize register (R/W: 34h/B4h) This register allows you to allocate the size of the ATL buffer to be used for ...

Page 104

NXP Semiconductors Code (Hex): 54 — read Code (Hex): D4 — write Table 97. HcATLBlkSize register: bit allocation Bit 15 Symbol Reset - Access - Bit 7 Symbol Reset 0 Access R/W R/W Table 98. Bit ...

Page 105

NXP Semiconductors Table 100. HcATLPTDSkipMap register: bit description Bit Symbol Access SkipBits R/W [31:0] 14.9.6 HcATLLastPTD register (R/W: 1Dh/9Dh) This is a 32-bit register. register represents the first PTD stored in the ATL buffer, bit 1 represents ...

Page 106

NXP Semiconductors 14.9.8 HcATLPTDDoneThresholdCount register (R/W: 51h/D1h) This register specifies the number of ATL PTDs to be done to trigger an ATL interrupt. If set to 08h, the Host Controller will trigger the ATL interrupt (in the Hc PInterrupt register) ...

Page 107

NXP Semiconductors Table 107. HcATLPTDDoneThresholdTimeOut register: bit description Bit 15. Peripheral Controller registers The functions and registers of the Peripheral Controller are accessed using commands, which consist of a command code followed by optional ...

Page 108

NXP Semiconductors Table 108. Peripheral Controller command and register overview Name Write or read DcInterruptEnable register Write or read DMA configuration Write or read DMA counter Reset device Data flow commands Write control OUT buffer Write control IN buffer Write ...

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NXP Semiconductors Table 108. Peripheral Controller command and register overview Name General commands Read control OUT error code Read control IN error code Read endpoint n error code ( 14) Unlock device Write or read DcScratch register ...

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NXP Semiconductors Table 109. DcEndpointConfiguration register: bit allocation Bit 7 Symbol FIFOEN EPDIR Reset 0 Access R/W R/W Table 110. DcEndpointConfiguration register: bit description Bit 15.1.2 DcAddress register (R/W: B7h/B6h) This command is ...

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NXP Semiconductors Code (Hex): B8/B9 — write or read DcMode register Transaction — write or read 1 byte (code or data) Table 113. DcMode register: bit allocation Bit 7 Symbol reserved [1] Reset 1 Access R/W R/W [1] Unchanged by ...

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NXP Semiconductors Bit 7 Symbol DAKOLY DRQPOL Reset 0 Access R/W R/W Table 116. DcHardwareConfiguration register: bit description Bit 15.1.5 DcInterruptEnable register (R/W: C3h/C2h) This ...

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NXP Semiconductors The command accesses the DcInterruptEnable register, which consists of 4 bytes. The bit allocation is given in Code (Hex): C2/C3 — write or read DcInterruptEnable register Transaction — write or read 4 bytes (code or data) Table 117. ...

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NXP Semiconductors Table 118. DcInterruptEnable register: bit description Bit 15.1.6 DcDMAConfiguration (R/W: F1h/F0h) This command defines the DMA configuration of the Peripheral Controller, and enables or disables DMA transfers. The command accesses the DcDMAConfiguration register, which consists ...

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NXP Semiconductors Table 120. DcDMAConfiguration register: bit description Bit 15.1.7 DcDMACounter register (R/W: F3h/F2h) This command accesses the DcDMACounter register, which consists of two bytes. The bit allocation is given in transfer. Reading the register ...

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NXP Semiconductors 15.2 Data flow commands Data flow commands are used to manage data transmission between USB endpoints and the system microprocessor. Much of the data flow is initiated using an interrupt to the microprocessor. Data flow commands are used ...

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NXP Semiconductors Table 124. Example of endpoint buffer memory access A0 HIGH LOW LOW LOW … Remark: There is no protection against writing or reading past a buffer’s boundary, against writing into an OUT buffer or reading from an IN ...

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NXP Semiconductors Table 126. DcEndpointStatus register: bit description Bit 15.2.3 Stall endpoint or unstall endpoint (40h to 4Fh/80h to 8Fh) These commands are used to stall or unstall an endpoint. The commands modify the content of ...

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NXP Semiconductors Code (Hex): 70 — clear endpoint buffer (control OUT, endpoints 1 to 14) Transaction — none (code only) 15.2.6 DcEndpointStatusImage register (D0h to DFh) This command is used to check the status of the selected ...

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NXP Semiconductors 15.3 General commands 15.3.1 Read endpoint error code (R: A0h to AFh) This command returns the status of the last transaction of the selected endpoint, as stored in the DcErrorCode register. Each new transaction overwrites the previous status ...

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NXP Semiconductors 15.3.2 Unlock Device (B0h) This command unlocks the Peripheral Controller from write-protection mode after a ‘resume’. In the ‘suspend’ state, all registers and buffer memory are write-protected to prevent data corruption by external devices during a ‘resume’. Also, ...

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NXP Semiconductors Table 135. DcScratch Information register: bit description Bit 15.3.4 DcFrameNumber register (R: B4h) This command returns the frame number of the last successfully received SOF followed by reading one word ...

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NXP Semiconductors Table 139. DcChipID register: bit allocation Bit 15 14 Symbol Reset 0 0 Access R R Bit 7 6 Symbol Reset 0 0 Access R R Table 140. DcChipID register: bit description Bit ...

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NXP Semiconductors Table 142. DcInterrupt register: bit description Bit ISP1362_5 Product data sheet Symbol Description - reserved EP14 to EP1 Logic 1 indicates the ...

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NXP Semiconductors 16. Limiting values Table 143. Limiting values In accordance with the Absolute Maximum Rating System (IEC 60134). Symbol Parameter V supply voltage CC V input voltage I I latch-up current lu V electrostatic discharge voltage esd T storage ...

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NXP Semiconductors 18. Static characteristics Table 145. Static characteristics: supply pins 3.6 V; GND = Symbol Parameter I operating supply current for CC(HC) the Host Controller I operating supply current for ...

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NXP Semiconductors Table 147. Static characteristics: analog I/O pins (D 3 3.6 V; GND = Symbol Parameter Input levels V differential input sensitivity DI V differential common mode CM voltage ...

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NXP Semiconductors Table 148. Static characteristics: charge pump 3.6 V; GND = Symbol Parameter I suspend supply current for CC(cp)(susp) charge pump I operating supply current in CC(cp) charge pump mode ...

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NXP Semiconductors V BUS (V) Fig 29. Output voltage as a function of load current ISP1362_5 Product data sheet 5 3 3.3 V 3.0 V 5.0 4.8 4 charge pump capacitor. ...

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NXP Semiconductors 19. Dynamic characteristics Table 149. Dynamic characteristics 3.6 V; GND = Symbol Parameter Reset t pulse width on input RESET W(RESET) Crystal oscillator f crystal frequency xtal R series ...

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NXP Semiconductors Table 151. Dynamic characteristics: charge pump 3.6 V; GND = Symbol Parameter t V pulsing time VBUS(PULSE) BUS t V pull-down time VBUS(VALID_dly) BUS V output ripple with constant ...

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NXP Semiconductors 15 data D [ 15:0 ] valid Fig 30. Host Controller programmed interface timing 19.1.2 Peripheral Controller programmed I/O timing Table 153. Dynamic characteristics: Peripheral Controller programmed interface timing ...

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NXP Semiconductors Table 153. Dynamic characteristics: Peripheral Controller programmed interface timing 3.6 V; GND = Symbol Parameter t chip deselect time after WR HIGH WHSH t data set-up time before WR ...

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NXP Semiconductors A0 (2) CS/DACK2 WR t DVWH D[15:0] (1) For t , both CS and WR must be de-asserted. SHWL (2) Programmable polarity: shown as active LOW. Fig 32. Peripheral Controller programmed interface write timing (I/O and 8237 compatible ...

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NXP Semiconductors DREQ1 DACK1 D [ 15:0 ] (read 15:0 ] (write Fig 33. Host Controller single-cycle DMA timing 19.2.2 Host Controller burst mode DMA timing Table 155. Dynamic characteristics: Host Controller burst mode DMA ...

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NXP Semiconductors DREQ1 t RHSH t RHAL DACK1 Fig 34. Host Controller burst mode DMA timing 19.2.3 Peripheral Controller single-cycle DMA timing (8237 mode) Table 156. Dynamic characteristics: Peripheral Controller single-cycle DMA timing (8237 mode ...

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NXP Semiconductors DREQ2 (1) DACK2 DATA (1) Programmable polarity: shown as active LOW. Fig 36. Peripheral Controller single-cycle DMA read timing in DACK-only mode 19.2.5 Peripheral Controller single-cycle DMA write timing in DACK-only mode Table 158. Dynamic characteristics: Peripheral Controller ...

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NXP Semiconductors 19.2.6 Peripheral Controller burst mode DMA timing Table 159. Dynamic characteristics: Peripheral Controller burst mode DMA timing 3.6 V; GND = Symbol Parameter t input RD/WR HIGH after DREQ ...

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NXP Semiconductors 20. Package outline LQFP64: plastic low profile quad flat package; 64 leads; body 1 pin 1 index DIMENSIONS (mm are the original ...

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NXP Semiconductors TFBGA64: plastic thin fine-pitch ball grid array package; 64 balls; body 0.8 mm ball A1 index area ball index area ...

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NXP Semiconductors 21. Soldering This text provides a very brief insight into a complex technology. A more in-depth account of soldering ICs can be found in Application Note AN10365 “Surface mount reflow soldering description” . 21.1 Introduction to soldering Soldering ...

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NXP Semiconductors 21.4 Reflow soldering Key characteristics in reflow soldering are: • Lead-free versus SnPb soldering; note that a lead-free reflow process usually leads to higher minimum peak temperatures (see reducing the process window • Solder paste printing issues including ...

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NXP Semiconductors Fig 41. Temperature profiles for large and small components For further information on temperature profiles, refer to Application Note AN10365 “Surface mount reflow soldering description” . 22. Abbreviations Table 162. Abbreviations Acronym ACK ASIC ATL ATX CMOS CRC ...

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NXP Semiconductors Table 162. Abbreviations Acronym HNP INTL IS ISO ISR ISTL LS MOSFET MSB NAK OHCI OPR OTG PDA PID PIO PLL PMOS POR PORP POST PTD RISC SIE SOF SRP TD USB USBD 23. References [1] On-The-Go Supplement ...

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NXP Semiconductors 24. Revision history Table 163. Revision history Document ID Release date ISP1362_5 20070508 • Modifications: The format of this data sheet has been redesigned to comply with the new presentation and information standard of NXP Semiconductors. • Legal ...

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NXP Semiconductors Table 163. Revision history …continued Document ID Release date ISP1362-04 20041224 (9397 750 13957) ISP1362-03 20040106 (9397 750 12337) ISP1362-02 20030219 (9397 750 10767) ISP1362-01 20021120 (9397 750 10087) ISP1362_5 Product data sheet Data sheet status Change notice ...

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NXP Semiconductors 25. Legal information 25.1 Data sheet status [1][2] Document status Product status Objective [short] data sheet Development Preliminary [short] data sheet Qualification Product [short] data sheet Production [1] Please consult the most recently issued document before initiating or ...

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NXP Semiconductors 27. Tables Table 1. Ordering information . . . . . . . . . . . . . . . . . . . . .4 Table 2. Pin description . . . . . . . ...

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NXP Semiconductors Table 91. HcINTLPTDSkipMap register: bit description 101 Table 92. HcINTLLastPTD register: bit description . . . .101 Table 93. HcINTLCurrentActivePTD register: bit allocation . . . . . . . . . . . . . . . ...

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NXP Semiconductors 28. Figures Fig 1. Block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . .5 Fig 2. Pin configuration ...

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NXP Semiconductors 29. Contents 1 General description . . . . . . . . . . . . . . . . . . . . . . 1 2 Features . . . . . . . . ...

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NXP Semiconductors 12.3 Endpoint description . . . . . . . . . . . . . . . . . . . . 52 12.3.1 Endpoints with programmable buffer memory size . . . . . . . ...

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NXP Semiconductors 15.2.1 Write or read endpoint buffer (R/W: 10h,12h to 1Fh/01h to 0Fh 115 15.2.2 Read endpoint status (R: 50h to 5Fh ...

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