STW5093CYL ST-Ericsson Inc, STW5093CYL Datasheet - Page 4

• Manufacturer Part Number: STW5093CYL
• Description: IC FILTR/CODEC 14BIT AUD 30TSSOP
• Manufacturer: ST-Ericsson Inc
• Type: Stereo Audior

Specifications of STW5093CYL

• Data Interface: PCM Audio Interface
• Resolution (bits): 14 b
• Number Of Adcs / Dacs: 1 / 1
• Sigma Delta: No
• Voltage - Supply, Analog: 2.7 V ~ 3.3 V
• Voltage - Supply, Digital: 2.7 V ~ 3.3 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 30-TSSOP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

STw5093
PIN FUNCTION (continued)
4/34
N°
24
25
26
27
28
29
30
VCCIO
MCLK
GND
Pin
CO
D
D
FS
R
X
Power supply Input for the Digital I/O's.
Control data Output: Serial control/status information is shifted out from the STw5093 on this pin
when CS- is low on the falling edges of CCLK.
Ground: All digital signals are referenced to this pin.
Transmit Data ouput: Data is shifted out on this pin during the assigned transmit time slots.
Elsewhere DX output is in the high impedance state. In delayed and non-delayed normal frame
synchr. modes, voice data byte is shifted out from TRISTATE output DX at the MCLK on the
rising edge of MCLK, while in non-delayed reverse frame synchr mode voice data byte is shifted
out on the falling edge of MCLK.
Receive data input: Data is shifted in during the assigned Received time slots In delayed and
non-delayed normal frame synchr. modes voice data byte is shifted in at the MCLK frequency on
the falling edges of MCLK, while in non-delayed reverse frame synchr. mode voice data byte is
shifted in at the MCLK frequency on the rising edges of MCLK.
Frame Sync input: This signal is a 8kHz clock which defines the start of the transmit and receive
frames. Any of three formats may be used for this signal: non delayed normal mode, delayed
mode, and non delayed reverse mode.
Master Clock Input: This signal is used by the switched capacitor filters and the encoder/decoder
sequencing logic. Values must be 512 kHz, 1.536 MHz, 2.048 MHz or 2.56 MHz selected by
means of Control Register CR0. MCLK is used also to shift-in and out data.
Description