ISP1161ABD-S ST-Ericsson Inc, ISP1161ABD-S Datasheet - Page 17

• Manufacturer Part Number: ISP1161ABD-S
• Description: IC USB HOST CTRL FULL-SPD 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1161ABD-S

• Controller Type: USB 2.0 Controller
• Interface: Parallel
• Voltage - Supply: 3.3V, 5V
• Current - Supply: 47mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
9397 750 13962
Product data
Fig 16. Internal FIFO buffer RAM access cycle.
write command
(16 bits)
8.4 FIFO buffer RAM access by PIO mode
Since the ISP1161A internal memory is structured as a FIFO buffer RAM, the FIFO
buffer RAM is mapped to dedicated register fields. Therefore, accessing the internal
FIFO buffer RAM is similar to accessing the internal control registers in multiple data
phases.
Figure 16
write cycle, the microprocessor first writes the FIFO buffer RAM’s command code to
the command port, and then writes the data words one by one to the data port until
half of the transfer’s byte count is reached. The HcTransferCounter register (22H -
read, A2H - write) is used to specify the byte count of a FIFO buffer RAM’s read cycle
or write cycle. Every access cycle must be in the same access direction. The read
cycle procedure is similar to the write cycle.
For access to the DC FIFO buffer RAM access, see
Fig 15. Accessing DC control registers.
WR
RD
CS
D [ 15:0 ]
A1, A0
shows a complete access cycle of the HC internal FIFO buffer RAM. For a
FIFO buffer RAM access cycle (transfer counter = 2N)
read/write data
#1 (16 bits)
Rev. 03 — 23 December 2004
DC command
write
code
11
Full-speed USB single-chip host and device controller
read/write data
#2 (16 bits)
DC register data
(lower word)
read
write
write
read
10
Section
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
read/write data
#N (16 bits)
DC register data
13.
(upper word)
write
write
read
read
10
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