ISP1581BD-T ST-Ericsson Inc, ISP1581BD-T Datasheet - Page 36

• Manufacturer Part Number: ISP1581BD-T
• Description: IC USB CTRL HI-SPEED 64LQFP
• Manufacturer: ST-Ericsson Inc

Specifications of ISP1581BD-T

• Controller Type: USB Peripheral Controller
• Interface: PCI
• Voltage - Supply: 3 V ~ 3.6 V
• Current - Supply: 130mA
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 64-LQFP
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

Philips Semiconductors
Table 35:
9397 750 13462
Product data
Bit
Symbol
Reset
Bus reset
Access
DMA Hardware register: bit allocation
7
ENDIAN[1:0]
9.4.4 DMA Hardware register (address: 3CH)
R/W
00H
00H
Table 34:
[1]
[2]
[3]
[4]
The DMA Hardware register consists of 1 byte. The bit allocation is shown in
Table
This register determines the polarity of the bus control signals (EOT, DACK, DREQ,
DIOR, DIOW) and the DMA mode (master or slave). It also controls whether the
upper and lower parts of the data bus are swapped (bits ENDIAN[1:0]), for modes
GDMA (slave) and MDMA (master) only.
Bit
3 to 2
1
0
[1]
6
The DREQ pin will be driven only after you perform a write access to the DMA Configuration register.
That is, after you have configured the DMA Configuration register.
DREQ is asserted only if space (writing) or data (reading) is available in the FIFO.
This process is stopped when the transfer FIFO becomes empty.
PIO Read or Write that started using DMA Command Register only performs 16-bit transfer.
35.
Symbol
MODE[1:0]
-
WIDTH
DMA Configuration register: bit description
EOT_
POL
R/W
5
0
0
Rev. 06 — 23 December 2004
MASTER
R/W
4
0
0
Description
These bits only affect the GDMA (slave) and MDMA (master)
handshake signals:
00H — DIOR (master) or DIOW (slave): strobes data from the
DMA bus into the ISP1581; DIOW (master) or DIOR (slave):
puts data from the ISP1581 on the DMA bus
01H — DIOR (master) or DACK (slave) strobes the data from
the DMA bus into the ISP1581; DACK (master) or DIOR
(slave) puts the data from the ISP1581 on the DMA bus
02H — DACK (master and slave) strobes the data from the
DMA bus into the ISP1581 and also puts the data from the
ISP1581 on the DMA bus (This mode is applicable only to
16-bit DMA; this mode cannot be used for 8-bit DMA.)
03H — reserved.
reserved
This bit selects the DMA bus width for GDMA (slave) and
MDMA (master):
0 — 8-bit data bus
1 — 16-bit data bus.
ACK_
POL
R/W
3
0
0
Hi-Speed USB peripheral controller
DREQ_
POL
R/W
…continued
2
1
1
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
WRITE_
POL
R/W
1
0
0
ISP1581
READ_
POL
R/W
0
0
0
35 of 79