DP83902AVLJ National Semiconductor, DP83902AVLJ Datasheet - Page 33

• Manufacturer Part Number: DP83902AVLJ
• Description: IC CTRLR SER NETWORK IN 100PQFP
• Manufacturer: National Semiconductor

Specifications of DP83902AVLJ

• Controller Type: Serial Network Interface Controller
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 140mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83902AVLJ

10 0 Internal Registers
10 3 REGISTER DESCRIPTIONS (Continued)
RECEIVE STATUS REGISTER (RSR)
This register records status of the received packet including information on errors and the type of address match either
physical or multicast The contents of this register are written to buffer memory by the DMA after reception of a good packet If
packets with errors are to be saved the receive status is written to memory at the head of the erroneous packet if an erroneous
packet is received If packets with errors are to be rejected the RSR will not be written to memory The contents will be cleared
when the next packet arrives CRC errors Frame Alignment errors and missed packets are counted internally by the ST-NIC
which relinguishes the Host from reading the RSR in real time to record errors for Network Management Functions The
contents of this register are not specified until after the first reception
Note Following coding applies to CRC and FAE bits
FAE
Bit
D0
D1
D2
D3
D4
D5
D6
D7
0
0
1
1
CRC
0
1
0
1
PRX
CRC
FAE
FO
MPA
PHY
DIS
DFR
Symbol
No Error (Good CRC and
CRC Error
Illegal Will Not Occur
Frame Alignment Error and CRC Error
Packet Received Intact Indicates packet received without error (Bits CRC FAE FO and MPA
are zero for the received packet )
CRC Error Indicates packet received with CRC error Increments Tally Counter (CNTR1) This
bit will also be set for Frame Alignment errors
Frame Alignment Error Indicates that the incoming packet did not end on a byte boundary and
the CRC did not match at the last byte boundary Increments Tally Counter (CNTR0)
FIFO Overrun This bit is set when the FIFO is not serviced causing overflow during reception
Reception of the packet will be aborted
Missed Packet Set when a packet intended for node cannot be accepted by ST-NIC because of
a lack of receive buffers or if the controller is in monitor mode and did not buffer the packet to
memory Increments Tally Counter (CNTR2)
Physical Multicast Address Indicates whether received packet had a physical or multicast
address type
0 Physical Address Match
1 Multicast Physical Address Match
Receiver Disabled Set when receiver disabled by entering Monitor mode Reset when receiver
is re-enabled when exiting Monitor mode
Deferring Set when internal Carrier Sense or Collision signals are generated in the ENDEC
module If the transceiver has asserted the CD line as a result of the jabber this bit will stay set
indicating the jabber condition
Type of Error
DFR
7
(Continued)
0CH (READ)
DIS
k
6
6 Dribble Bits)
PHY
5
MPA
4
33
FO
3
Description
FAE
2
CRC
1
PRX
0