DP83902AVLJ National Semiconductor, DP83902AVLJ Datasheet - Page 44

• Manufacturer Part Number: DP83902AVLJ
• Description: IC CTRLR SER NETWORK IN 100PQFP
• Manufacturer: National Semiconductor

Specifications of DP83902AVLJ

• Controller Type: Serial Network Interface Controller
• Interface: Serial
• Voltage - Supply: 4.75 V ~ 5.25 V
• Current - Supply: 140mA
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 100-MQFP, 100-PQFP
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Other names: *DP83902AVLJ

5 The ST-NIC holds onto the bus for the entire sequence
13 0 Bus Arbitration and Timing
mine whether the packet matches its Physical Address Reg-
isters or maps to one of its Multicast Registers This causes
the FIFO to accumulate 8 bytes Furthermore there are
some synchronization delays in the DMA PLA Thus the
actual time that BREQ is asserted from the time the Start of
Frame Delimiter (SFD) is detected is 7 8 s This operation
affects the bus latencies at 2- and 4-byte thresholds during
the first receive BREQ since the FIFO must be filled to 8
bytes (or 4 words) before issuing a BREQ
FIFO Operation at the End of Receive
When Carrier Sense goes low the ST-NIC enters its end of
packet processing sequence emptying its FIFO and writing
the status information at the beginning of the packet Figure
The longest time BREQ may be extended occurs when a
packet ends just as the ST-NIC performs its last FIFO burst
The ST-NIC in this case performs a programmed burst
transfer followed by flushing the remaining bytes in the
FIFO and completes by writing the header information to
memory The following steps occur during this sequence
1 ST-NIC issues BREQ because the FIFO threshold has
2 During the burst packet ends resulting in BREQ extend-
3 ST-NIC flushes remaining bytes from FIFO
4 ST-NIC performs internal processing to prepare for writ-
5 ST-NIC writes 4-byte (2-word) header
6 ST-NIC deasserts BREQ
been reached
ed
ing the header
End of Packet Processing
(Continued)
44
End of Packet Processing (EOPP) times for 10 MHz and
20 MHz have been tabulated in the table below
Threshold Detection (Bus Latency)
To assure that no overwriting of data in the FIFO occurs the
FIFO logic flags a FIFO overrun as the 13th byte is written
into the FIFO effectively shortening the FIFO to 13 bytes
The FIFO logic also operates differently in Byte Mode and in
Word Mode In Byte Mode a threshold is indicated when
the n
threshold the ST-NIC issues Bus Request (BREQ) when
the 9th byte has entered the FIFO For Word Mode BREQ
is not generated until the n
Thus with a 4-word threshold (equivalent to 8-byte thresh-
old) BREQ is issued when the 10th byte has entered the
FIFO The two graphs following indicate the maximum al-
lowable bus latency for Word and Byte transfer modes
Mode
Byte
Byte
Word
Word
End of Packet Processing Times for Various FIFO
a
Thresholds Bus Clocks and Transfer Modes
1 byte has entered the FIFO thus with an 8-byte
Threshold
2 Bytes
4 Bytes
8 Bytes
2 Bytes
4 Bytes
8 Bytes
2 Bytes
4 Bytes
8 Bytes
2 Bytes
4 Bytes
8 Bytes
a
2 bytes have entered the FIFO
Bus Clock
10 MHz
20 MHz
10 MHz
20 MHz
TL F 11157 – 58
7 0 s
8 6 s
11 0 s
3 6 s
4 2 s
5 0 s
5 4 s
6 2 s
7 4 s
3 0 s
3 2 s
3 6 s
EOPP