DP83902AVLJ National Semiconductor, DP83902AVLJ Datasheet - Page 34
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DP83902AVLJ
Manufacturer Part Number
DP83902AVLJ
Description
IC CTRLR SER NETWORK IN 100PQFP
Manufacturer
National Semiconductor
Datasheet
1.DP83902AVJGNOPB.pdf
(70 pages)
Specifications of DP83902AVLJ
Controller Type
Serial Network Interface Controller
Interface
Serial
Voltage - Supply
4.75 V ~ 5.25 V
Current - Supply
140mA
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Package / Case
100-MQFP, 100-PQFP
Lead Free Status / RoHS Status
Contains lead / RoHS non-compliant
Other names
*DP83902AVLJ
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10 0 Internal Registers
10 4 DMA REGISTERS
The DMA Registers are partitioned into groups Transmit
Receive and Remote DMA Registers The Transmit regis-
ters are used to initialize the Local DMA Channel for trans-
mission of packets while the Receive Registers are used to
initialize the Local DMA Channel for packet Reception The
Page Stop Page Start Current and Boundary Registers are
used by the Buffer Management Logic to supervise the Re-
ceive Buffer Ring The Remote DMA Registers are used to
initialize the Remote DMA
Note In the figure above registers are shown as 8 or 16 bits wide Although
10 5 TRANSMIT DMA REGISTERS
TRANSMIT PAGE START REGISTER (TPSR)
This register points to the assembled packet to be transmit-
ted Only the eight higher order addresses are specified
since all transmit packets are assembled on 256-byte page
boundaries The bit assignment is shown below The values
placed in bits D7–D0 will be used to initialize the higher
order address (A8 –A15) of the Local DMA for transmission
The lower order bits (A7–A0) are initialized to zero
some registers are 16-bit internal registers all registers are accessed
as 8-bit registers Thus the 16-bit Transmit Byte Count Register is
broken into two 8-bit registers TBCR0 TBCR1 Also TPSR PSTART
PSTOP CURR and BNRY only check or control the upper 8 bits of
address information on the bus Thus they are shifted to positions
15–8 in the diagram above
(Continued)
DMA Registers
34
TRANSMIT BYTE COUNT REGISTER 0 1
(TBCR0 TBCR1)
These two registers indicate the length of the packet to be
transmitted in bytes The count must include the number of
bytes in the source destination length and data fields The
maximum number of transmit bytes allowed is 64 Kbytes
The ST-NIC will not truncate transmissions longer than
1500 bytes The bit assignment is shown below
TBCR1
TBCR0
TPSR
Bit Assignment
(A7–A0 Initialized to Zero)
A15 A14 A13 A12 A11 A10
L15
L7
7
7
7
L14
L6
6
6
6
L13
L5
5
5
5
L12
L4
4
4
4
TL F 11157 – 19
L11
L3
3
3
3
L10
L2
2
2
2
A9
L9
L1
1
1
1
A8
L8
L0
0
0
0